llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-05 17:30:02 +00:00

Author	SHA1	Message	Date
Joe Abbey	895ede819f	Commit test, capitalizing store... keep it simple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142336 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-18 04:44:36 +00:00
Eli Friedman	0851a29b6d	Fix misc warnings. Patch by Joe Abbey. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-18 03:17:34 +00:00
Lang Hames	d8ffe5bb16	Backing out patch. Will refactor to remove the AsmParser dependency on Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142323 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-18 00:23:49 +00:00
Jim Grosbach	6248a546f2	ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-18 00:22:00 +00:00
Lang Hames	5fa792e65a	Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies. Thanks to Raphael Espindola for tracking down the CMake issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142306 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 23:24:48 +00:00
Jim Grosbach	ea46110f57	ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 23:09:09 +00:00
Nick Lewycky	44d798d976	Add support for a new extension to the .file directive: .file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 23:05:28 +00:00
Chad Rosier	3a7572ff61	Add a few FIXME comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142299 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:54:23 +00:00
Jim Grosbach	fa1ee88052	Tidy up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:41:42 +00:00
Rafael Espindola	10820d9a97	142288 broke the build: Linking CXX executable ../../bin/llvm-as ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' clang-3: error: linker command failed with exit code 1 (use -v to see invocation) Revert "Validate target data layout strings." This reverts commit `599d2d4c25`. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142296 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:37:51 +00:00
Bill Wendling	13a7121858	Now Igor, throw the switch...give my creation life! Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:26:23 +00:00
Jim Grosbach	0e387b2877	ARM NEON "vmov.i8" immediate assembly parsing and encoding. NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:26:03 +00:00
Lang Hames	599d2d4c25	Validate target data layout strings. Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142288 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 22:05:34 +00:00
Benjamin Kramer	d2c6ff1ac6	Use a SmallVector for intrinsic argument types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142259 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 21:33:26 +00:00
Bill Wendling	a48ed4fc8f	Don't renumber the blocks here. This could cause problems later on if another pass renumbers the blocks again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 21:32:56 +00:00
Cameron Zwarich	6f9c28060f	Pseudoinstructions should not be less constrained than the instruction they are lowered to. This fixes a lot of verifier failures on the test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 21:20:13 +00:00
Jim Grosbach	698f3b068f	Tidy up organization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142248 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 21:00:11 +00:00
Bill Wendling	5bc85286ff	Add a call to EmitSjLjDispatchBlock. Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 20:37:20 +00:00
Jim Grosbach	32ab4aff69	Fix improperly formed assert() call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142239 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 20:22:59 +00:00
Akira Hatanaka	8ae330ac90	Add definitions of conditional moves with 64-bit operands. Comment out code for expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:53:29 +00:00
Hal Finkel	c61291609d	Revert change to function alignment b/c existing logic was fine git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:53:03 +00:00
Chad Rosier	c378015d1c	Removed set, but unused variables. Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:48:30 +00:00
Akira Hatanaka	8f3af87e99	Move class and instruction definitions for conditional moves to a seperate file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:43:19 +00:00
Akira Hatanaka	eea367ec97	Revert change made in r142205. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142217 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:33:24 +00:00
Akira Hatanaka	bdfd98a080	Redefine count-leading 0s and 1s instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:26:37 +00:00
Akira Hatanaka	89d306669e	Redefine mfhi/lo and mthi/lo instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:24:15 +00:00
Akira Hatanaka	f1fddcd9e0	Redefine multiply and divide instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:21:24 +00:00
Akira Hatanaka	2d0a61da62	Add definition of a base class for logical shift/rotate instructions with two source registers and redefine 32-bit and 64-bit instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:17:58 +00:00
Hal Finkel	e9e5791556	Remove >80-col line and unicode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142209 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:10:08 +00:00
Akira Hatanaka	363934665d	Add definition of a base class for logical shift/rotate immediate instructions and have 32-bit and 64-bit instructions derive from it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:06:56 +00:00
Akira Hatanaka	a01820a508	Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 18:01:00 +00:00
Michael J. Spencer	9904056a70	Fix CMake build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 17:50:39 +00:00
Devang Patel	827454e6e2	svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp There is no reason to have simple IR level pass in lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 17:17:43 +00:00
Hal Finkel	98daa9dcc8	Instructions for Book E PPC should be word aligned, set function alignment to reflect this git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 17:01:41 +00:00
Craig Topper	4b2dc74d3f	Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142177 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 05:33:10 +00:00
Bill Wendling	24bb925566	Add comment explaining that the order of processing doesn't matter here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 05:25:09 +00:00
Hal Finkel	b31d3d271f	Add PPC 440 scheduler and some associated tests (new files) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 04:03:55 +00:00
Hal Finkel	c6d08f10bf	Add PPC 440 scheduler and some associated tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-17 04:03:49 +00:00
Craig Topper	ee62e4f6d1	Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 16:50:08 +00:00
Benjamin Kramer	5efabcf01d	Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing. <stdin>:1:12: error: register %rax is only available in 64-bit mode incl %rax ^~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142137 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 12:10:27 +00:00
Benjamin Kramer	f82edaffb1	X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands. <stdin>:1:4: error: invalid instruction mnemonic 'abc' abc incl %edi ^~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142135 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 11:28:29 +00:00
Nadav Rotem	c32a8c9073	Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was no pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 10:02:06 +00:00
Craig Topper	b53fa8bf19	Add X86 BZHI instruction as well as BMI2 feature detection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 07:55:05 +00:00
Craig Topper	dc479c4a89	Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 07:05:40 +00:00
Cameron Zwarich	daada347b5	Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. These missing flags show up as errors when running -verify-coalescing on test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 06:38:10 +00:00
Cameron Zwarich	d575137634	Fix an obvious typo found when looking at nearby code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 06:38:06 +00:00
Chris Lattner	d8b7aa2613	Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 04:47:35 +00:00
Craig Topper	17730847d5	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 03:51:13 +00:00
Craig Topper	4145c49aa0	Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-16 00:21:51 +00:00
Craig Topper	566f233ba6	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 20:46:47 +00:00
Nadav Rotem	4d83b79c76	The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142081 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 20:05:17 +00:00
Nadav Rotem	004a24b44c	ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 20:03:12 +00:00
Benjamin Kramer	003fad98cc	SmallVector -> array git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142073 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 13:28:31 +00:00
Jakob Stoklund Olesen	534849687c	Mark tADDrSPi as having side effects again. It really doesn't, but when r141929 removed the hasSideEffects flag from this instruction, it caused miscompilations. I am guessing that it got moved across a stack pointer update. Also clear isRematerializable after checking that this instruction is in fact never rematerialized in the nightly test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 00:57:13 +00:00
Chad Rosier	d73462a1c9	Thumb1 does not support dynamic stack realignment. rdar://10288916 is tracking this fix. In the past, instcombine and other passes were promoting alloca alignment past the natural alignment, resulting in dynamic stack realignment. Lang's work now prevents this from happening (LLVM commit r141599). Now that this really shouldn't happen report a fatal error rather than silently generate bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 00:28:24 +00:00
Bill Wendling	918f2155e9	Mark registers as DEAD because they're really just clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-15 00:27:44 +00:00
Eli Friedman	46995fa7e2	Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 23:58:49 +00:00
Bill Wendling	5d79859f66	Make sure that the register is in the register class before adding it as a machine op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 23:55:44 +00:00
Bill Wendling	969c9ef0dd	Mark the invoke call instruction as implicitly defining the callee-saved registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 23:34:37 +00:00
Richard Trieu	8223e45dff	Fix a non-firing assert. Change: assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 20:50:26 +00:00
Evan Cheng	b10946a5a9	A few 80-col violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141988 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 20:36:23 +00:00
Hal Finkel	d712f935f7	Add an implementation of the CanLowerReturn function to the PPC backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141981 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 19:51:36 +00:00
Akira Hatanaka	1ce2668c84	Add f128 to datalayout string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141978 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 19:14:50 +00:00
Hal Finkel	8ee53e2eb6	initial test commit (remove whitespace) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141972 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 18:54:13 +00:00
Akira Hatanaka	008b58c4ae	Revert r141932, r141936 and r141937. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141959 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 17:16:39 +00:00
Craig Topper	54a11176f6	Add X86 ANDN instruction. Including instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 07:06:56 +00:00
Craig Topper	909652f687	Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 03:21:46 +00:00
Akira Hatanaka	91d2cc9cdd	Definition of function getMipsRegisterNumbering. Patch by Jack Carter and Reed Kotler at Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141938 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 03:04:24 +00:00
Akira Hatanaka	2891662cc2	Add definition of class MipsELFWriterInfo. Patch by Jack Carter and Reed Kotler at Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141937 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 02:55:47 +00:00
Akira Hatanaka	51f72c5a3f	Add missing relocation types. Patch by Jack Carter and Reed Kotler at Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141936 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 02:47:50 +00:00
Akira Hatanaka	36004b93ef	Fixup enumerations. Patch by Jack Carter at Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141934 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 02:38:56 +00:00
Akira Hatanaka	93d2a0a1fa	Add more Mips relocation types. Patch by Jack Carter at Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141932 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 02:17:30 +00:00
Jakob Stoklund Olesen	ccbe603869	Ban rematerializable instructions with side effects. TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 01:00:49 +00:00
Jakob Stoklund Olesen	0a951fba75	V_SET0 has no side effects. TableGen will mark any pattern-less instruction as having unmodeled side effects. This is extra bad for V_SET0 which gets rematerialized a lot. This was part of the cause for PR11125, but the real bug was fixed in r141923. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141924 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-14 00:39:50 +00:00
Eli Friedman	ecb830e45c	Fix undefined shift. Patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 23:36:06 +00:00
Eli Friedman	d83a54fd35	Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141912 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 23:27:48 +00:00
Eli Friedman	5bd7ff2128	Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141909 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 23:13:35 +00:00
Eli Friedman	8e4d0429de	Simplify and avoid undefined shift. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141903 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 22:40:23 +00:00
Owen Anderson	c18e940c5a	SETEND is not allowed in an IT block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 17:58:39 +00:00
Kalle Raiskila	898f336c51	Mark 'branch indirect' instruction as an indirect branch. Not having it confused assembly printing of jumptables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 11:40:03 +00:00
Bill Wendling	4e68054b20	More closely follow libgcc, which has code after the `ret' instruction to release the stack segment and reset the stack pointer. Place the code in its own MBB to make the verifier happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 08:24:19 +00:00
Bill Wendling	1203fe7fc8	Revert r141854 because it was causing failures: http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 07:48:07 +00:00
Bill Wendling	82222c20be	Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 07:42:32 +00:00
Craig Topper	8ab1d1e900	Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 07:09:14 +00:00
Craig Topper	d501c714cd	Add 'implicit EFLAGS' to patterns for popcnt and lzcnt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141853 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-13 06:18:52 +00:00
Jim Grosbach	81b2928d80	ARM addrmode5 represents the 'U' bit of the encoding backwards. The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 21:59:02 +00:00
Jim Grosbach	c66e7afcf2	Thumb2 assembly parsing and encoding for LDC/STC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 20:54:17 +00:00
Jim Grosbach	b0786b33fa	addrmode2 is gone from these, so no need for the reg0 operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 18:11:24 +00:00
Jim Grosbach	9b8f2a0b36	ARM parsing and encoding for the <option> form of LDC/STC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 17:34:41 +00:00
Jim Grosbach	01208d56e8	80 columns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 16:36:01 +00:00
Jim Grosbach	bc9c80240b	Tidy up. Formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 16:34:37 +00:00
Akira Hatanaka	41f9a430cb	Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 01:05:13 +00:00
Akira Hatanaka	6baabc1dd0	Fix encoding of 32-bit integer instructions. Change names of operands and nodes. Remove unused classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141757 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 00:56:06 +00:00
Nick Lewycky	1f9c6860bf	Fix indent in comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141749 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 00:14:12 +00:00
Jakob Stoklund Olesen	1c062c24ab	Fix -widen-vmovs liveness issues. When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141746 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-12 00:06:23 +00:00
Akira Hatanaka	80eb994929	Change name of class to ArithOverflowR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 23:43:48 +00:00
Akira Hatanaka	2dfd3a9789	Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical instructions with two register operands derive from it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141742 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 23:38:52 +00:00
Akira Hatanaka	76d9f1c022	Fix comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141737 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 23:12:12 +00:00
Akira Hatanaka	c2f3ac9de2	Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit arithmetic and logical instructions with three register operands derive from them. Fix instruction encoding too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141736 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 23:05:46 +00:00
Akira Hatanaka	68ad5673e8	Fix function isUnalignedLoadStore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141722 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 22:04:01 +00:00
Jim Grosbach	2bd0118472	ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 21:55:36 +00:00
Akira Hatanaka	d8212b2916	Remove unused PatLeaf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141720 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 21:53:08 +00:00
Akira Hatanaka	7cc037a137	Change the names of 64-bit logical instructions so that they match the names of the real instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141718 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 21:48:01 +00:00
Bill Wendling	e575499d83	Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 21:40:47 +00:00
Akira Hatanaka	395d76c5a3	Remove redundancy in setcc patterns using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141715 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 21:40:01 +00:00
Akira Hatanaka	b07a3d6897	Use sltiu instead of sltu when a register operand and immediate are compared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 20:44:43 +00:00
Jim Grosbach	2cf8dd384e	ARM addressing mode cleanup for LDC/STC. We parse at least some forms of the instructions now. Encoding is pretty screwed up, still, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 20:17:35 +00:00
Akira Hatanaka	06f8231bfb	Add patterns for conditional branches with 64-bit register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141696 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 19:09:09 +00:00
Akira Hatanaka	8191f34797	Add support for 64-bit set-on-less-than instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 18:53:46 +00:00
Akira Hatanaka	3e3427a5c3	Add support for conditional branch instructions with 64-bit register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 18:49:17 +00:00
Jim Grosbach	57dcb85a30	ARM parse alignment specifier for NEON load/store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 17:29:55 +00:00
Jim Grosbach	e53c87b302	ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 15:59:20 +00:00
Richard Osborne	6c6f28ffe4	Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks. This fixes an assert due to the operands of the DBG_VALUE instruction not being as expected (PR11105). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141666 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 12:55:35 +00:00
Kalle Raiskila	56354d48bb	Fix a iterator out of bounds error, that triggers rarely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 12:55:18 +00:00
Craig Topper	c48b301fb0	Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141656 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 07:13:09 +00:00
Craig Topper	227358e93c	Make Ivy Bridge 16-bit floating point conversion instructions require AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141654 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 07:01:37 +00:00
Craig Topper	37f2167f15	Add X86 LZCNT instruction. Including instruction selection support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 06:44:02 +00:00
Craig Topper	29480fd798	Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 04:34:23 +00:00
Akira Hatanaka	1acb7df498	Make changes necessary for supporting floating point load and store instructions that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 01:12:52 +00:00
Jakob Stoklund Olesen	142bd1a54e	Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo(). The VMOVS widening needs to look at the implicit COPY operands. Trying to dig out the COPY instruction from an iterator in copyPhysReg() is the wrong approach. The expandPostRAPseudo() hook gets to look at COPY instructions before they are converted to copyPhysReg() calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141619 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:59:06 +00:00
Akira Hatanaka	a5903acd6b	Modify lowering of GlobalAddress so that correct code is emitted when target is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:55:05 +00:00
Lang Hames	4ad06e61c0	Fixed natural stack alignment for Linux x86-32. Thanks Eli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141616 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:51:36 +00:00
Akira Hatanaka	381e97dcf6	Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141615 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:44:20 +00:00
Akira Hatanaka	43aed32e20	Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:37:28 +00:00
Akira Hatanaka	7bd19bd519	Add definitions of 64-bit loads and stores. Add a patterns for unaligned zextloadi32 for which there is no corresponding pseudo or real instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:27:28 +00:00
Akira Hatanaka	d55bb38ddc	Change definitions of classes LoadM and StoreM in preparation for adding support for 64-bit load and store instructions. Add definitions of 64-bit memory operand and 16-bit immediate operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141603 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:11:12 +00:00
Bill Wendling	3f56d4b957	Simplify check that optional def is there and is CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-11 00:10:41 +00:00
Lang Hames	bb5b3f3359	Add a natural stack alignment field to TargetData, and prevent InstCombine from promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 23:42:08 +00:00
Jim Grosbach	f6c35c59f5	Simplify operand Kind checks a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 23:06:42 +00:00
Bill Wendling	ef2c86f876	Reapply r141365 now that PR11107 is fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 22:59:55 +00:00
Jim Grosbach	38fbe32315	Add a name to sub-operand for clarity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 22:55:05 +00:00
Bill Wendling	721e1d2669	If the CPSR is defined by a copy, then we don't want to merge it into an IT block. E.g., if we have: movs r1, r1 rsb r1, 0 movs r2, r2 rsb r2, 0 we don't want this to be converted to: movs r1, r1 movs r2, r2 itt mi rsb r1, 0 rsb r2, 0 PR11107 & <rdar://problem/10259534> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 22:52:53 +00:00
Eli Friedman	dca62d53b7	Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 22:28:47 +00:00
Benjamin Kramer	717073c237	X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 19:35:07 +00:00
Nadav Rotem	a7934dd8e4	Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the instruction set has no 64-bit SRA support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 19:31:45 +00:00
Benjamin Kramer	a86a58695d	X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 18:34:56 +00:00
Bill Wendling	eba564ceac	Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to hang, and possibly SPEC/CINT2006/464_h264ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 18:27:30 +00:00
Bill Wendling	8129d21396	When getting the number of bits necessary for addressing mode ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 07:24:23 +00:00
Craig Topper	1f104804bf	Put a bunch of calls to ToggleFeature behind proper if statements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141527 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 05:34:02 +00:00
Chad Rosier	29b9d7e4ea	Fix a regression from r138445. If we're loading from the frame/base pointer the tADDrSPi instruction can't be used. Make sure we're updating the opcode to tADDi3 in all cases. rdar://10254707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141523 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-10 01:03:35 +00:00
Justin Holewinski	68226a4d46	PTX: Print .ptr kernel attributes if PTX version >= 2.2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141508 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-09 15:42:02 +00:00
Craig Topper	da394041c4	Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen	b7994fedcb	Prevent potential NOREX bug. A GR8_NOREX virtual register is created when extrating a sub_8bit_hi sub-register: %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1 TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2 If such a live range is ever split, its register class must not be inflated to GR8. The sub-register copy can only target GR8_NOREX. I dont have a test case for this theoretical bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141500 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen	ed74482704	Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 18:28:28 +00:00
Nicolas Geoffray	f8557957fb	Always check if a method or a type exist before trying to create it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141490 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 11:56:36 +00:00
Anton Korobeynikov	2d4b60f3a4	Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 08:38:45 +00:00
Akira Hatanaka	4391bb75ec	Simplify definition of FP move instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 03:50:18 +00:00
Akira Hatanaka	c9289f6a71	Define classes and multiclasses for FP binary instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 03:38:41 +00:00
Akira Hatanaka	bfca0798cf	Define multiclasses for FP-to-FP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 03:29:22 +00:00
Akira Hatanaka	a8de1c1be0	Define classes for FP unary instructions and multiclasses for FP-to-fixed point conversion instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 03:19:38 +00:00
Akira Hatanaka	cb518ee5dd	Add patterns for unaligned load and store instructions and enable the instruction selector to generate them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141471 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-08 02:24:10 +00:00
Jim Grosbach	460a90540b	ARM NEON assembly parsing and encoding for VDUP(scalar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 23:56:00 +00:00
Jim Grosbach	21ff17ce1b	ARM prefix asmparser operand kind enums for readability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 23:24:09 +00:00
Bill Wendling	2acf638216	Take all of the invoke basic blocks and make the dispatch basic block their new successor. Remove the old landing pad from their successor list, because it's now the successor of the dispatch block. Now that the landing pad blocks are no longer the destination of invokes, we can mark them as normal basic blocks instead of landing pads. This more closely resembles what the CFG is actually doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 23:18:02 +00:00
Bill Wendling	f1083d4139	Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit it with the new SjLj emitter stuff. This way there's no need to emit that kind-of-hacky intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 22:08:37 +00:00
Bill Wendling	ce370cfd89	Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 21:25:38 +00:00
Jakob Stoklund Olesen	b66f18486a	Constrain both operands on MOVZX32_NOREXrr8. This instruction is explicitly encoded without an REX prefix, so both operands but be *_NOREX. Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX constraints are not satisfied. This fixes a miscompilation in 20040709-2 in the gcc test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 20:15:54 +00:00
Jim Grosbach	186ffac4d3	Improve ARM assembly parser diagnostic for unexpected tokens. Consider: mov r8, r11 fred Previously, we issued the not very informative: x.s:6:1: error: unexpected token in argument list ^ Now we generate: x.s:5:14: error: unexpected token in argument list mov r8, r11 fred ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 18:27:04 +00:00
Evan Cheng	7c1780c5fe	High bits of movmskp{s\|d} and pmovmskb are known zero. rdar://10247336 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 17:21:44 +00:00
Bob Wilson	6d2f9cec71	Reenable tail calls for iOS 5.0 and later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 17:17:49 +00:00
Bob Wilson	2fef4573df	Reenable use of divmod compiler_rt functions for iOS 5.0 and later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 16:59:21 +00:00
Anton Korobeynikov	244455e6d6	Peephole optimization for ABS on ARM. Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 16:15:08 +00:00
Craig Topper	75fe5f3bab	Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 07:02:24 +00:00
Craig Topper	1b526a98e3	Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 05:53:50 +00:00
Craig Topper	25f6dfd108	Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-07 05:35:38 +00:00
Bill Wendling	217f0e9ca4	Use the correct vreg here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 23:41:14 +00:00
Bill Wendling	083a8eb063	Generate the dispatch code for a 'thumb' function. This is very similar to the others. They take the call site value. Determine if it's a proper value. And then jumps to the correct call site via a jump table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 23:37:36 +00:00
Owen Anderson	7011eee9b5	Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 23:33:11 +00:00
Eli Friedman	8540101252	Remove the old atomic instrinsics. autoupgrade functionality is included with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 23:20:49 +00:00
Bill Wendling	95ce2e9c52	Generate the dispatch table for ARM mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 22:53:00 +00:00
Bill Wendling	e29fa1df55	Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 22:18:16 +00:00
Bill Wendling	5e2cbc1133	Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!) Place the immediate to OR into a register so that it works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 21:51:21 +00:00
Bill Wendling	04f15b4f2f	* Set the low bit of the return address when we are in thumb mode. * Some code cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 21:29:56 +00:00
Justin Holewinski	9a6eba6203	PTX: Implement signed division git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141306 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 20:00:33 +00:00
Craig Topper	7ea16b01fa	Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 06:44:41 +00:00
Peter Collingbourne	de8f33c199	Build system infrastructure for multiple tblgens. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 01:51:51 +00:00
Bill Wendling	930193cb55	Add the MBBs before inserting the instructions. Doing it afterwards could lead to an infinite loop because of the def-use chains. Also use a frame load instead of store for the LD instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-06 00:53:33 +00:00
Cameron Zwarich	8f8aa815b4	Always merge profitable shifts on A9, not just when they have a single use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 23:39:02 +00:00
Cameron Zwarich	d78ebe1e12	Remove a check from ARM shifted operand isel helper methods, which were blocking merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 23:38:50 +00:00
Bill Wendling	5cbef19a1d	Get the proper call site numbers for the landing pads. Also remove a magic number (18) for the proper addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 23:28:57 +00:00
Jakob Stoklund Olesen	9bb272c900	Override TRI::getSubClassWithSubReg for X86. There are fewer registers with sub_8bit sub-registers in 32-bit mode than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as sub_8bit_hi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 20:26:33 +00:00
Justin Holewinski	591c1c6754	PTX: Fixup a case where getRegClassFor() should be used instead of custom code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141199 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 18:32:25 +00:00
Akira Hatanaka	42be280a28	Fix assertion string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141197 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 18:17:49 +00:00
Akira Hatanaka	41a796e9cc	Make sure candidate for delay slot filler is not a return instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141196 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 18:16:09 +00:00
Akira Hatanaka	2f52338f50	Add RA to the set of registers that are defined if instruction is a call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141194 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 18:11:44 +00:00
Owen Anderson	2dbb46a0a0	Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 17:16:40 +00:00
Duncan Sands	62c607b741	Ensure OpCode is not used uninitialized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141184 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 15:13:13 +00:00
Duncan Sands	72478e6046	Comment out a variable that is only used in commented out code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141183 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 15:12:44 +00:00
Duncan Sands	37f80658b3	Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141182 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 15:11:08 +00:00
NAKAMURA Takumi	4cbc5a1118	MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141174 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 10:11:02 +00:00
Cameron Zwarich	fb77752253	Add braces around something that throws me for a loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141173 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 08:59:10 +00:00
Cameron Zwarich	5ee0262014	There is no point in setting out-parameters for a ComplexPattern function when it returns false, at least as far as I could tell by reading the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141172 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 08:59:05 +00:00
Craig Topper	41e59c7c34	Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141162 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 03:29:32 +00:00
Akira Hatanaka	176965f46b	Insert space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141158 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 02:22:49 +00:00
Akira Hatanaka	6e4e64859f	Do not examine variadic or implicit operands if instruction is a return (jr). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141157 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 02:21:58 +00:00
Akira Hatanaka	0c419a7c4b	Clean up function Filler::delayHasHazard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141156 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 02:18:58 +00:00
Akira Hatanaka	0f0c59a0f8	Remove function Filler::insertCallUses. Record the registers used and defined by a call in Filler::insertDefsUses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141154 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 02:04:17 +00:00
Akira Hatanaka	7d8e04d5f1	Clean up Filler::findDelayInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141152 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:57:46 +00:00
Akira Hatanaka	53120e0a9f	Remove function Filler::isDelayFiller. Check if I is the same instruction that filled the last delay slot visited. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141151 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:30:09 +00:00
Akira Hatanaka	6f818abbe3	Clean up Filler::runOnMachineBasicBlock. Change interface of Filler::findDelayInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141150 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:23:39 +00:00
Akira Hatanaka	98f4d4d2db	Define a statistic for the number of slots that were filled with useful instructions (instructions that are not NOP). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141149 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:19:13 +00:00
Akira Hatanaka	f2f70c2493	Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before I->getDesc().hasDelaySlot() does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141148 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:15:31 +00:00
Akira Hatanaka	cfc3fb5737	Add comments and move assignment statement. If sawStore is true, sawLoad does not have to be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141147 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:09:37 +00:00
Akira Hatanaka	6585b51821	Correct description string of enable-mips-delay-filler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141146 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 01:06:57 +00:00
Bill Wendling	bb73468e2b	Look at the number of entries in the jump table and jump to a 'trap' block if the value exceeds that number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 00:39:32 +00:00
Bill Wendling	2a85015313	Checkpoint for SJLJ EH code. This is a first pass at generating the jump table for the sjlj dispatch. It currently generates something plausible, but hasn't been tested thoroughly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-05 00:02:33 +00:00
Owen Anderson	2fec6c5ff1	Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 23:26:17 +00:00
Kevin Enderby	9e5887b17e	Adding back support for printing operands symbolically to ARM's new disassembler using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 22:44:48 +00:00
Jakob Stoklund Olesen	01faf432d9	Teach PPCInstrInfo to handle sub-classes. This has already been done for most other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 15:28:47 +00:00
Nadav Rotem	34804c4f47	Set operation actions to legal types only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 12:05:35 +00:00
Nadav Rotem	e8783096d2	Operations should be custom lowered only if their type is legal. Test: CellSPU/v2i32.ll when running with -promote-elements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 10:03:32 +00:00
Craig Topper	6744a17dcf	Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-04 06:30:42 +00:00
Jim Grosbach	9d39036f62	ARM assembly parsing and encoding for VMOV immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 23:38:36 +00:00
Jim Grosbach	2a3f19d7e3	Tidy up. 80 columns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 23:03:26 +00:00
Bill Wendling	ff4216a68a	Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 22:44:15 +00:00
Jim Grosbach	68259145d9	ARM parsing/encoding for VCMP/VCMPE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 22:30:24 +00:00
Bill Wendling	f7e4aefd0f	Check-pointing the new SjLj EH lowering. This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 21:25:38 +00:00
Akira Hatanaka	43e43f7d8b	Add support for 64-bit logical NOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 21:23:18 +00:00
Akira Hatanaka	2d57088ff0	Add support for 64-bit count leading ones and zeros instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 21:16:50 +00:00
Jim Grosbach	5cd5ac6ad4	ARM assembly parsing and encoding for VMRS/FMSTAT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 21:12:43 +00:00
Akira Hatanaka	dda4a07cd8	Add support for 64-bit divide instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 21:06:13 +00:00
Jim Grosbach	b95ed6ec46	Thumb2 ADD/SUB can take SP as a destination register. It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 20:51:59 +00:00
Akira Hatanaka	2ad766851d	Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 20:38:08 +00:00
Akira Hatanaka	04d3762ff1	Add support for 64-bit integer multiply instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 20:01:11 +00:00
Akira Hatanaka	36787939b2	Add definitions of instructions which move values between 64-bit integer registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 19:28:44 +00:00
Craig Topper	581fe82c84	Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 17:28:23 +00:00
Rafael Espindola	25456ef74c	Add the returns_twice attribute to LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 14:45:37 +00:00
Craig Topper	04c5be9f12	Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 08:14:29 +00:00
Craig Topper	7b22976de3	Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-03 07:51:09 +00:00
Craig Topper	82f131a017	Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-02 21:08:12 +00:00
Craig Topper	146c6d77f0	Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-02 16:56:09 +00:00
Craig Topper	846a2dcada	Fix disassembling of INVEPT and INVVPID to take operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 21:20:14 +00:00
Craig Topper	e1b4a1a07e	Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 19:54:56 +00:00
Chad Rosier	2bfaf521ae	Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." to appease nightly testers. Not quite there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 19:30:36 +00:00
Bill Wendling	2e6b97bbf8	No one should be using the method directly. Assert if they do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 12:47:34 +00:00
Bill Wendling	405ca137a1	Add a convenience method to tell if two things are equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 12:44:28 +00:00
Bill Wendling	3320f2a3bf	Use the ARMConstantPoolMBB class to handle the MBB values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 09:30:42 +00:00
Bill Wendling	9c18f51daa	Add ARMConstantPoolMBB to hold an MBB value in the constant pool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 09:19:10 +00:00
Bill Wendling	14a1a6b018	Remove dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 09:05:12 +00:00
Bill Wendling	9aca75c4f8	Remove now dead methods and ivar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 09:04:18 +00:00
Bill Wendling	fe31e67350	Use the new ARMConstantPoolSymbol class to handle external symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 08:58:29 +00:00
Bill Wendling	ff4a8023ec	Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140938 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 08:36:59 +00:00
Bill Wendling	3f4e4592c3	Remove now dead methods and ivar from ARMConstantPoolValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140937 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 08:02:05 +00:00
Bill Wendling	5bb779976a	Switch over to using ARMConstantPoolConstant for global variables, functions, and block addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 08:00:54 +00:00
Bill Wendling	3e944e38ea	Some more refactoring. * Add a couple of Create methods to the ARMConstantPoolConstant class, * Add its own version of getExistingMachineCPValue, and * Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140935 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 07:52:37 +00:00
Bill Wendling	029e93888d	Add a Create method that accepts 'kind' and 'pcadj' arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140934 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 06:44:24 +00:00
Bill Wendling	f2b76aae2b	Refactoring: Separate out the ARM constant pool Constant from the ARM constant pool value. It's not used right now, but will be soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140933 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 06:40:33 +00:00
Chad Rosier	5249041125	Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8	2011-10-01 02:03:18 +00:00
Jakob Stoklund Olesen	c8e2bb68bb	Store sub-class lists as a bit vector. This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen	e27e1ca3c9	Move getCommonSubClass() into TRI. It will soon need the context. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 22:18:51 +00:00
Jim Grosbach	f391e9f696	Correct for my over-eager delete finger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 22:02:45 +00:00
Akira Hatanaka	09a2e0f794	Register the MC object streamer. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140887 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 21:29:38 +00:00
Akira Hatanaka	4b6ee7a352	Register Asm backend. Add functions to MipsAsmBackend. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140886 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 21:23:45 +00:00
Akira Hatanaka	82ea7314ca	Add MCELFObjectTargetWriter and MCAsmBackend classes. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140885 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 21:04:02 +00:00
Benjamin Kramer	310c9ea874	Update CMake build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140879 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 20:44:33 +00:00
Akira Hatanaka	4520a10fdb	Initial implementation of MipsMCCodeEmitter. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140878 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 20:40:03 +00:00
Akira Hatanaka	c7bafe9241	Add definitions of Mips64 rotate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 18:51:46 +00:00
Bill Wendling	d98f838284	Constify 'isLSDA' and move a method out-of-line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140868 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 18:42:06 +00:00
Jim Grosbach	6f09fcf5da	ARM Darwin default relocation model is PIC. This matches clang, so default options in llc and friends are now closer to clang's defaults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 17:41:35 +00:00
Akira Hatanaka	a64556ffda	isCommutable should be 0 for DSUBu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140862 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 17:26:36 +00:00
Jim Grosbach	98602ac9a9	ARM Fixup valus for movt/movw are for the whole value. Remove an assert that was expecting only the relevant 16bit portion for the fixup being handled. Also kill some dead code in the T2 portion. rdar://9653509 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 17:23:05 +00:00
Justin Holewinski	f51b7e5d74	PTX: Various stylistic and code readability changes recommended by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140855 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 14:36:36 +00:00
Justin Holewinski	8c1dac54f2	PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs. Also take this opportunity to clean up the rounding mode pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140854 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 13:46:52 +00:00
Justin Holewinski	c90e149ee4	PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires us to manually provide Pat<> definitions for all FP instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140849 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 12:54:43 +00:00
Akira Hatanaka	25a7d94e81	Mips64 shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 03:18:46 +00:00
Akira Hatanaka	f549ab7853	Mips64 arithmetic and logical instructions with one source register and immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 02:08:54 +00:00
Jim Grosbach	4ebbf7b8a8	ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-30 00:50:06 +00:00
Akira Hatanaka	a3defb07a0	Fill delay slot with useful instructions. Modified from Sparc's version of delay slot filler. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 23:52:13 +00:00
Bill Wendling	e00897c5a9	Create a machine basic block in the constant pool and retrieve the symbol for an MBB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140824 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 23:50:42 +00:00
Bill Wendling	4dd9b091cc	Support creating a constant pool value for a machine basic block. This is used when we want to take the address of a machine basic block, but it's not associated with a BB in LLVM IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140823 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 23:48:44 +00:00
Akira Hatanaka	c0be26909f	Mips64 arithmetic and logical instructions with two source registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 20:37:56 +00:00
Eli Friedman	bb5a7442e3	Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140803 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 20:21:17 +00:00
Justin Holewinski	2097d702d4	PTX: Fix broken shared library build git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140783 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 14:25:48 +00:00
Jakob Stoklund Olesen	92fb79b7a6	Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 05:10:54 +00:00
NAKAMURA Takumi	13f4a6c940	Target/ARM: Unbreak! CMake! Build! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen	adcb634d85	Delete NEONMoveFix, now unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen	8bb3d3cb30	Use ExecutionDepsFix instead of NEONMoveFix. This enables NEON domain tracking across basic blocks, but should otherwise do the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 02:48:41 +00:00
Bill Wendling	3511cedf36	Move to ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 01:13:55 +00:00
Justin Holewinski	d57c1bc0b6	PTX: Add new patterns for bitconvert and any_extend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-29 01:13:12 +00:00
Jakob Stoklund Olesen	5cd4ee7770	Revert r140731, "Define classes for unary and binary FP instructions and use them to define" It broke the unit tests. Please reapply with tests fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 23:59:28 +00:00
Evan Cheng	9b88d2d782	Tighten a ARM dag combine condition to avoid an identity transformation, which ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 23:16:31 +00:00
Akira Hatanaka	d42ca4607b	Define classes for unary and binary FP instructions and use them to define multiclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 21:58:01 +00:00
Eli Friedman	7d3e2b78c7	PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 21:00:25 +00:00
Bill Wendling	b18abd077e	Perform the lowering only if there are invokes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 20:29:45 +00:00
Bill Wendling	39689c8154	Ahem...actually add the ARMSjLjLowering pass to the pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 20:29:28 +00:00
Justin Holewinski	cfab2be391	PTX: Fix alignment logic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140709 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 18:24:58 +00:00
Akira Hatanaka	aa7579025f	Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140705 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 18:11:19 +00:00
Akira Hatanaka	d9f958375f	Remove definitions of branch-on-FP-likely instructions. They are deprecated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140704 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 17:56:55 +00:00
Akira Hatanaka	d2d00edc01	Mips64 predicate definitions. Patch by Liu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 17:50:27 +00:00
Justin Holewinski	ed0e4c85c4	PTX: MC-ize the PTX backend (patch 2 of N) Get rid of some of the no-longer-needed parts of PTXAsmPrinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140698 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 14:32:06 +00:00
Justin Holewinski	d8e4ed2686	PTX: MC-ize the PTX back-end (patch 1 of N) Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 14:32:04 +00:00
James Molloy	acad68da50	Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a slightly different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 14:21:38 +00:00
Benjamin Kramer	ca9215970d	PTX: Simplify code. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140680 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 04:32:36 +00:00
Benjamin Kramer	8adae0c940	PTX: Pass param name strings per const reference. The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140679 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 04:08:02 +00:00
Jakob Stoklund Olesen	d4d4fca9c3	Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix. I'll clean up the source in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 00:01:54 +00:00
Akira Hatanaka	6c6db25c10	Remove MipsFPRound. Mips1 is no longer supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140661 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 23:55:37 +00:00
Jakob Stoklund Olesen	df4b35e3dd	Remove X86-dependent stuff from SSEDomainFix. This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 23:50:46 +00:00
Ted Kremenek	833217bfb9	Unbreak CMake build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen	13fd601e0f	Implement TII::get/setExecutionDomain() for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 22:57:21 +00:00
Jakob Stoklund Olesen	98e933f9ad	Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo. I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 22:57:18 +00:00
Jim Grosbach	25ddc2bf7e	ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 22:18:54 +00:00
Bill Wendling	0481d29d49	This is the start of the new SjLj EH preparation pass, which will replace the current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 22:14:12 +00:00
Akira Hatanaka	8eea4616bf	Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside of the instruction definitions using Pat<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 22:01:01 +00:00
Jim Grosbach	5405d58e21	Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). Naming conventions consistency. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 20:59:33 +00:00
Justin Holewinski	332850d8cc	PTX: Fix case where printed alignment could be 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140624 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 19:25:49 +00:00
Justin Holewinski	f47dfba023	PTX: Use external symbols to keep track of params and locals. This also fixes a couple of outstanding issues with frame objects occuring as instruction operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140616 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 18:12:55 +00:00
Jakob Stoklund Olesen	8e695eb5fa	Use existing function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 17:55:08 +00:00
Akira Hatanaka	237e7a278a	Fix function MipsRegisterInfo::getRegisterNumbering. Return numbers of 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 17:15:27 +00:00
Akira Hatanaka	78fec58c07	Do not add the pass that restores $gp if target is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140607 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 16:58:43 +00:00
Akira Hatanaka	854222fa47	Mark MipsPseudo isPseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 04:57:54 +00:00
Justin Holewinski	13e0c805a2	PTX: Add support for sitofp in backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-27 01:04:47 +00:00
Owen Anderson	2dafe200ca	Remove extraneous commit garbage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 23:14:02 +00:00
Akira Hatanaka	f40de9d287	Set register class of a register according to value of HasMips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 21:55:17 +00:00
Akira Hatanaka	8b4198da9d	Define variable HasMips64 in MipsTargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 21:47:02 +00:00
Akira Hatanaka	09dd60feef	In single float mode, double precision FP arguments are passed in integer registers, so there is no need to check here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 21:37:50 +00:00
Owen Anderson	0afa0094af	ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 21:06:22 +00:00
Justin Holewinski	22d54da918	PTX: Fix memcpy intrinsic to handle 64-bit pointers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140556 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 19:19:48 +00:00
Justin Holewinski	bc97f4402b	PTX: Implement PTXSelectionDAGInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140549 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 18:57:27 +00:00
Justin Holewinski	63bce90c0d	PTX: Implement ISD::ANY_EXTEND git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140548 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 18:57:24 +00:00
Justin Holewinski	63602ed876	PTX: Fix detection of stack load/store vs. global load/store, as well as fix the printing of local offsets git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140547 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 18:57:22 +00:00
Justin Holewinski	22f3c59ec3	PTX: SM > 2.0 implies +double git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140536 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 16:20:36 +00:00
Justin Holewinski	58788503b8	PTX: Fix some lingering issues with stack allocation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140535 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 16:20:34 +00:00
Justin Holewinski	d5c3920f8d	PTX: Split up the TableGen instruction definitions into logical units git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140534 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 16:20:31 +00:00
Justin Holewinski	c1d8fbd41a	PTX: Unify handling of loads/stores git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140533 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 16:20:28 +00:00
Justin Holewinski	6b8990df42	PTX: Handle FrameIndex nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140532 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 16:20:25 +00:00
David Meyer	8f418b11d2	PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 06:13:20 +00:00
Craig Topper	100d86ada5	Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-26 05:12:43 +00:00
Jakob Stoklund Olesen	74e2d6ea66	Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-25 16:46:08 +00:00
Akira Hatanaka	8aa4b4cb6f	Add .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140446 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-24 01:40:18 +00:00
Akira Hatanaka	95934844e3	Preparation for adding simple Mips64 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-24 01:34:44 +00:00
Jakob Stoklund Olesen	51f0c76419	Only run MF.verify() with EXPENSIVE_CHECKS=1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140441 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-24 01:11:19 +00:00
Owen Anderson	4d2a00147d	Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen	11ebe3d7c1	Also match negative offsets for addrmode3 and addrmode5. Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 22:10:33 +00:00
Owen Anderson	4a713570b6	Add more fixed bits to USAT16 encoding to filter out incorrect decodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 21:57:50 +00:00
Owen Anderson	0781c1f700	Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 21:26:40 +00:00
Owen Anderson	31d485ec9a	Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 21:07:25 +00:00
Owen Anderson	df0caeb6ec	Revert r140412. This affects more instructions than intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 21:02:01 +00:00
Owen Anderson	d256056581	Thumb2 register-shifted-register loads cannot target the PC or the SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 21:00:32 +00:00
Akira Hatanaka	45b73e2f3f	Implement N32/64 calling convention. Patch by Liu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140401 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 19:08:15 +00:00
Akira Hatanaka	792016bc22	Make FGR64RegisterClass available if target is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 18:28:39 +00:00
Akira Hatanaka	b1dcff0fe3	Add definitions of 64-bit register files. Add code for returning Mips64's sets of callee-saved registers and reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 18:11:56 +00:00
Justin Holewinski	a5745569b6	PTX: Fix parameter order bug git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140394 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 17:59:11 +00:00
Wesley Peck	2e3441e5e5	Fix a couple of 80 column violations. patch contributed by Jia Liu! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140391 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 17:24:41 +00:00
Justin Holewinski	dc0baf9b40	PTX: Cleanup unused code in PTXMachineFunctionInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140390 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 17:15:53 +00:00
Justin Holewinski	d7070fe6df	PTX: Fix another 80-column violation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140387 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 16:50:35 +00:00
Justin Holewinski	75d809599b	PTX: Handle function call return values git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140386 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 16:48:41 +00:00
Richard Osborne	0353dab90e	Fix 80 column violations. Original patch by Liu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140385 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 16:28:10 +00:00
Duncan Sands	04aa4aee89	Implement Chris's suggestion of legalizing the various SSE and AVX hadd/hsub intrinsics into the new fhadd/fhsub X86 node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140383 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 16:10:22 +00:00
Justin Holewinski	e953a64cb5	PTX: Start fixing function calls git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140378 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 14:31:12 +00:00
Justin Holewinski	d3dec06447	PTX: Remove PTX calling convention files git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140377 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 14:18:27 +00:00
Justin Holewinski	1cde87d202	[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001 --- lib/Target/PTX/PTXInstrInfo.td \| 165 ++++++++++++++++++++---------- lib/Target/PTX/PTXIntrinsicInstrInfo.td \| 88 +++++++++++------ 2 files changed, 167 insertions(+), 86 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140376 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 14:18:24 +00:00
Justin Holewinski	27f08fc619	PTX: Generalize handling of .param types git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140375 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 14:18:22 +00:00
Justin Holewinski	04b5ebc74c	PTX: Cleanup unused code in the PTXMFInfoExtract pass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140374 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 14:18:19 +00:00
Akira Hatanaka	aaa9fc2e37	Add definitions of 64-bit int registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140366 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 02:33:15 +00:00
Akira Hatanaka	373e3a4091	Do not rely on the enum values of argument registers A0-A3 being consecutive. Define function getNextIntArgReg, which takes a register as a parameter and returns the next O32 argument integer register. Use this function when double precision floating point arguments are passed in two integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-23 00:58:33 +00:00
Eli Friedman	a6176adc8a	PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140355 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 23:41:28 +00:00
Akira Hatanaka	40eda4626d	Make changes in instruction and pattern definitions so that tablegen does not complain it cannot infer types in patterns. Fix a mistake in definition of SDT_MipsExtractElementF64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140354 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 23:31:54 +00:00
Jakob Stoklund Olesen	4bd89873be	Add support for GR32 <-> FR32 cross class copies. We already support GR64 <-> VR128 copies. All of these copies break partial register dependencies by zeroing the high part of the target register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140348 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 22:45:24 +00:00
Duncan Sands	17470bee5f	Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from floating point add/sub of appropriate shuffle vectors. Does not synthesize the 256 bit AVX versions because they work differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 20:15:48 +00:00
Akira Hatanaka	98f49c4413	Print parentheses in next line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140325 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 18:29:29 +00:00
Akira Hatanaka	ebb90dbb54	Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140324 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 18:24:21 +00:00
Akira Hatanaka	95a091a0b6	Define a new sub-register index sub_32 for accessing the 32-bit sub-register of a 64-bit integer register. Move the subreg index definitions to the beginning of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 17:57:32 +00:00
Akira Hatanaka	26bcc701a2	Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or VK_Mips_GPOFF_LO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140316 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 17:44:37 +00:00
Akira Hatanaka	d27fda49c4	Add F31 to the set of callee-saved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 17:35:03 +00:00
Akira Hatanaka	4e41416359	Fix typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140313 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 17:26:58 +00:00
Justin Holewinski	7c9dd62441	PTX: Remove physical register defs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140310 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:48 +00:00
Justin Holewinski	5422a0f166	PTX: Use .param space for device function return values on SM 2.0+, and attempt to fix up parameter passing on SM < 2.0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140309 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:46 +00:00
Justin Holewinski	05591be5ed	PTX: Fix style issues git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140308 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:43 +00:00
Justin Holewinski	297984d7c6	PTX: Fixup codegen to handle emission of virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140307 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:40 +00:00
Justin Holewinski	40466cc758	PTX: Customize codegen passes in backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140306 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:37 +00:00
Justin Holewinski	247ee00bce	PTX: Add new PTX-specific register allocator that keeps virtual registers instead of allocating physical registers. This is part of a work-in-progress overhaul of the PTX register allocation scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140305 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 16:45:33 +00:00
Craig Topper	adf01b3f18	Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 07:01:50 +00:00
Akira Hatanaka	bb7d289aeb	Add definition of 64-bit floating registers used for Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140297 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 03:48:47 +00:00
Benjamin Kramer	2c2ccbf108	The SSE version differences for fmin/fmax are more involved than I thought. - x87: no min or max. - SSE1: min/max for single precision scalars and vectors. - SSE2: min/max for single and double precision scalars and vectors. - AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140296 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 03:27:22 +00:00
Akira Hatanaka	e33ca9ce1f	Add enums and functions for symbols Mips64 uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 03:09:07 +00:00
Benjamin Kramer	74f3501d15	X86: Don't form min/max nodes if the target is missing SSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 03:01:42 +00:00
Akira Hatanaka	459cad2dfd	Mips64 aligns stack on 16-byte boundary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140292 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 02:53:37 +00:00
Akira Hatanaka	c56f5ea4c3	Remove unnecessary condition check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-22 02:41:29 +00:00
Owen Anderson	6126870193	Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 23:53:44 +00:00
Owen Anderson	e136872970	Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 23:44:46 +00:00
Benjamin Kramer	15c9a1f60c	X86Disassembler: if verbose logging is going to nulls(), disable logging completely. Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140276 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 21:47:35 +00:00
Wesley Peck	91b60c1487	Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile. patch contributed by Jia Liu! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140273 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 19:23:46 +00:00
Owen Anderson	519020adf1	These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 17:58:45 +00:00
Akira Hatanaka	0e64f810a5	Undo a change made in r140254. MipsArchVersion needs to be initialized to Mips32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 17:31:45 +00:00
Nadav Rotem	64ac73bb15	fix comment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140258 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 17:14:40 +00:00
Akira Hatanaka	47c40a2cf9	MipsArchVersion does not need to be in the initialization list and MipsABI should be initialized to UnknownABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 16:41:43 +00:00
Nadav Rotem	9c6cdf4c1c	Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140246 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 08:45:10 +00:00
Richard Trieu	23946fcaae	Change: assert(!"error message"); To: assert(0 && "error message"); which is more consistant across the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140234 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 03:09:09 +00:00
Akira Hatanaka	2464810ac2	Add a base class for Mips TargetMachines and add Mips64 TargetMachines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 03:00:58 +00:00
Akira Hatanaka	8c1b4bf066	Set ABI if it hasn't been set on the command line. Check if architecture & ABI combination is valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 02:45:29 +00:00
Akira Hatanaka	50fa74e8d2	Fix typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140229 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 02:24:25 +00:00
Andrew Trick	3be654f808	Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 02:20:46 +00:00
Andrew Trick	e23dc9c0ef	whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140227 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 02:17:37 +00:00
Owen Anderson	317eaf1993	In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-21 00:25:23 +00:00
Akira Hatanaka	5663344127	Change the names of functions isMips* to hasMips*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 23:53:09 +00:00
Bruno Cardoso Lopes	f4b841d4e2	Revert r140097, working on a better approach git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 23:19:29 +00:00
Bruno Cardoso Lopes	149f29f1fd	Simplify max/minp[s\|d] dagcombine matching git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 22:34:45 +00:00
Bruno Cardoso Lopes	4e42335972	Tidy up a bit more, fix tab and remove trailing whitespaces git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140186 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes	448d986858	The wrong relocation was being emitted for several SSSE3 instructions. This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes	77169a9197	Tidy up code! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140183 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 21:39:06 +00:00
Evan Cheng	0d18174f0f	Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 21:38:18 +00:00
Akira Hatanaka	1daa5bea58	Initial Mips64 support. Patch by Liu with some modifications. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140178 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 20:28:08 +00:00
Andrew Trick	83a8031336	Restore hasPostISelHook tblgen flag. No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 18:22:31 +00:00
Craig Topper	3699261d3f	Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 07:38:59 +00:00
Andrew Trick	4815d56bb2	ARM isel bug fix for adds/subs operands. Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 03:17:40 +00:00
Andrew Trick	3af7a67629	whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 03:06:13 +00:00
Jim Grosbach	50f1c37123	Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:46:54 +00:00
Jim Grosbach	6053cd956f	Thumb2 assembly parsing and encoding for USAX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:30:45 +00:00
Jim Grosbach	8c9898454c	Remove incorrect comments. These are not disassmebly only patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:26:34 +00:00
Jim Grosbach	ab3bf97fe0	Thumb2 assembly parsing and encoding for UQASX/UQSAX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:18:52 +00:00
Jim Grosbach	abb8aacef2	Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140108 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:10:37 +00:00
Jim Grosbach	26215425da	Thumb CPS definition is not disassembler only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-20 00:00:06 +00:00
Jim Grosbach	0efe213ed5	Thumb2 range check on CPS mode immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:58:31 +00:00
Owen Anderson	d9346fbb06	tMOVSr is not allowed in an IT block either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:57:20 +00:00
Owen Anderson	9f666b5f2e	CPS instructions are UNPREDICTABLE inside IT blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:47:10 +00:00
Jim Grosbach	32f36899e9	Tidy up comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:38:34 +00:00
Bruno Cardoso Lopes	d91c6e058b	Fix PR10949. Fix the encoding of VMOVPQIto64rr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes	97136c922e	Based on the small opt Zvi's patch was trying to achieve, eliminate 128-bit undef subvector insertion into a 256-bit vector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140097 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:36:50 +00:00
Jim Grosbach	d5d0e81a4b	Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:31:02 +00:00
Jim Grosbach	6729c48b94	Thumb2 assembly parsing and encoding for UHASX/UHSAX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:13:25 +00:00
Jim Grosbach	4032eaf98c	Thumb2 assembly parsing and encoding for UASX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 23:05:22 +00:00
Owen Anderson	04c7877894	Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 22:34:23 +00:00
Jim Grosbach	7f739bee26	Thumb2 assembly parsing and encoding for TBB/TBH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 22:21:13 +00:00
Bruno Cardoso Lopes	97dc60b759	Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix PR10955 and PR10948. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140069 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 21:29:24 +00:00
Jim Grosbach	bc80e94865	Tidy up a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 20:31:59 +00:00
Jim Grosbach	326efe5891	Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 20:29:33 +00:00
Akira Hatanaka	da7f5f1c1d	Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't yet legal according to comments in LegalizeDAG.cpp:227. Memcpy nodes created for copying byval arguments are inserted before CALLSEQ_START. The two failing tests reported in PR10876 pass after applying this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140046 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 20:26:02 +00:00
Owen Anderson	061c3c4506	Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 20:00:02 +00:00
Jim Grosbach	fb12f35545	ARM asm parsing should handle pre-indexed writeback w/o immediate. For example, 'ldrb r9, [sp]!' is odd, but valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 18:42:21 +00:00
Owen Anderson	ecd1c55790	Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 18:07:10 +00:00
Jim Grosbach	8a8d28b039	Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-19 17:56:37 +00:00
Nadav Rotem	ca6f296b48	Fix typos in my prev commit, found by Tobi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-18 19:00:23 +00:00
Nadav Rotem	354efd88db	setOperationAction should be done on the return value of the type, not the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140001 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-18 14:57:03 +00:00
Nadav Rotem	91e43fd17a	When promoting integer vectors we often create ext-loads. This patch adds a dag-combine optimization to implement the ext-load efficiently (using shuffles). For example the type <4 x i8> is stored in memory as i32, but it needs to find its way into a <4 x i32> register. Previously we scalarized the memory access, now we use shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139995 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-18 10:39:32 +00:00
Craig Topper	89af15ee11	Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139993 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-18 08:03:58 +00:00
Duncan Sands	6bcd2196e5	Synthesize x86 max/min instructions also for vectors (i.e. produce maxps and maxpd). This broke the sse41-blend.ll testcase by causing maxpd to be produced rather than a cmp+blend pair, which is the reason I tweaked it. Gives a small speedup on doduc with dragonegg when the GCC vectorizer is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-17 16:49:39 +00:00
Bruno Cardoso Lopes	2c693dc126	Describe more AVX 128-bit convert instructions without patterns to have mayLoad = 1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139973 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 23:41:29 +00:00
Owen Anderson	cb77551927	Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 23:30:01 +00:00
Owen Anderson	8b22778431	Fix bitfield decoding based on Eli's feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 23:04:48 +00:00
Jim Grosbach	f67e8554bf	Thumb2 assembly parsing and encoding for SUB(immediate). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 22:58:42 +00:00
Owen Anderson	e4f2df945a	Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 22:42:36 +00:00
Owen Anderson	89db0f690c	Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 22:29:48 +00:00
Owen Anderson	8a28bdcbcc	Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 22:17:02 +00:00
Bruno Cardoso Lopes	7291272ab2	Add mayLoad attribute to AVX convert instructions, since non of them are declared with load patterns. This fix the crash in PR10941. No testcases, since a fold is triggered and then converted back to the register form afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139953 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 22:02:14 +00:00
Jim Grosbach	ee2c2a4f98	Thumb2 assembly parsing and encoding for STR. More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 21:55:56 +00:00
Jim Grosbach	947a24cd64	Tidy up. 80 columns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 21:09:00 +00:00
Owen Anderson	705b48ff86	Fix disassembly of Thumb2 LDRSH with a #-0 offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 21:08:33 +00:00
Jim Grosbach	642caea2c6	Thumb2 assembly parsing and encoding for STR(immediate). Add aliases for STRB/STRH while there. Tests forthcoming for those. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 21:06:12 +00:00
Bruno Cardoso Lopes	08ecb711ac	Fix PR10884. This PR basically reports a problem where a crash in generated code happened due to %rbp being clobbered: pushq %rbp movq %rsp, %rbp .... vmovmskps %ymm12, %ebp .... movq %rbp, %rsp popq %rbp ret Since Eric's r123367 commit, the default stack alignment for x86 32-bit has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass hasn't been really used, but with AVX it becomes useful again, since per ABI compliance we don't always align the stack to 256-bit, but only when there are 256-bit incoming arguments. ReserveFP was only used by this pass, but there's no RA target hook that uses getReserveFP() to check for the presence of FP (since nothing was triggering the pass to run, the uses of getReserveFP() were removed through time without being noticed). Change this pass to use setForceFramePointer, which is properly called by MachineFunction hasFP method. The testcase is very big and dependent on RA, not sure if it's worth adding to test/CodeGen/X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139939 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 20:58:28 +00:00
Jim Grosbach	8213c96655	Thumb2 assembly parsing and encoding for STMIA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-16 20:50:13 +00:00

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