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1968 Commits

Author SHA1 Message Date
Owen Anderson
c6788c83b4 t2SMLAD is a four-register instruction, not a three-register one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe Correct operand naming of t2USAT16 to allow proper decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:27:47 +00:00
Owen Anderson
2379fc235f Match operand naming to allow correct decoding of t2LDRSH_POST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:22:05 +00:00
Jim Grosbach
6dcafc0d0b Improve error checking for tPUSH and tPOP register lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:17:34 +00:00
Jim Grosbach
762f70bc49 Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:13:54 +00:00
Owen Anderson
2c9f83533b Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:10:16 +00:00
Jim Grosbach
0c2165bbd0 Thumb parsing and encoding for PUSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:05:11 +00:00
Jim Grosbach
10fd9ad8f3 Fix think-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:04:26 +00:00
Jim Grosbach
7260c6a4ea Thumb assemmbly parsing diagnostic improvements for LDM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:01:07 +00:00
Jim Grosbach
d937d95125 Thumb assembly parsing and encoding for POP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 23:00:19 +00:00
Owen Anderson
838130e3b9 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 21:34:00 +00:00
Owen Anderson
357ec6850b Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:27:12 +00:00
Owen Anderson
2cbf210450 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:22:06 +00:00
Owen Anderson
88b7ccc7f0 Port another swathe of Thumb1 encoding tests over to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 18:05:49 +00:00
Owen Anderson
b113ec55e8 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:56:58 +00:00
Jim Grosbach
011af5ca80 Thumb assembly parsing and encoding for ORR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 17:41:44 +00:00
Jim Grosbach
fbe1681490 Fix AsmParser binary precedence for shift operators. 
rdar://9976729



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 16:24:13 +00:00
Jim Grosbach
2f4bdc5db9 Tidy up. Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138207 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-20 16:10:09 +00:00
Jim Grosbach
0780b6303b Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 23:24:36 +00:00
Jim Grosbach
2c3f70e5d4 Thumb assembly parsing and encoding for NEG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:51:03 +00:00
Jim Grosbach
7a01069420 Be more lenient on tied operand matching for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes
0c9acfcb50 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:27:29 +00:00
Jim Grosbach
c4762a9c91 Thumb assembly parsing and encoding for MVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:09:23 +00:00
Jim Grosbach
88ae2bc6d5 Thumb assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 22:07:46 +00:00
Jim Grosbach
584fb0e663 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:48:54 +00:00
Jim Grosbach
4ec6e888ec Thumb assembly parsing and encoding for MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 20:46:54 +00:00
Jim Grosbach
c7ebca335d Thumb assembly parsing and encoding for LSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:34:22 +00:00
Jim Grosbach
560ef9f2fe Thumb assembly parsing and encoding for LSL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:30:58 +00:00
Jim Grosbach
1b7b68f087 Thumb assembly parsing and encoding for LSL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:29:25 +00:00
Jim Grosbach
05b0156734 Thumb assembly parsing and encoding for LDRSB and LDRSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 19:17:58 +00:00
Jim Grosbach
38466309d5 Thumb assembly parsing and encoding for LDRH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:55:51 +00:00
Jim Grosbach
48ff5ffe9e Thumb assembly parsing and encoding for LDRB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:49:59 +00:00
Jim Grosbach
09f6e0dfda Thumb assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:35:06 +00:00
Jim Grosbach
67b95f902a Thumb assembly parsing and encoding for LDR(literal). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:20:48 +00:00
Jim Grosbach
ecd8589683 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 18:13:48 +00:00
Jim Grosbach
60f91a3d95 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 17:55:24 +00:00
Craig Topper
e004d941ec Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes
863e0f25b7 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 02:23:56 +00:00
Owen Anderson
78affc9ea1 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:31:17 +00:00
Owen Anderson
14090bf263 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:11:02 +00:00
Jim Grosbach
93b3eff623 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 21:50:53 +00:00
Owen Anderson
847a7ad800 More Thumb1 decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 20:05:06 +00:00
Jim Grosbach
1eba8a66b6 Thumb assembly parsing and encoding for EOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:10:38 +00:00
Jim Grosbach
0d1511c022 Thumb assembly parsing and encoding for CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:08:29 +00:00
James Molloy
dbe46744c5 Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:03:02 +00:00
Jim Grosbach
7750b8df6a Thumb assembly parsing and encoding test for CMN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137957 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:55:03 +00:00
Owen Anderson
7cf6d7a083 Port over BL/BLX to disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:43:52 +00:00
Jim Grosbach
6ea80e964b ARM assembly parsing and encoding test for BX/BLX (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:02:28 +00:00
Jim Grosbach
ded439886a ARM assembly parsing and encoding test for BL/BLX (immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:00:09 +00:00
Owen Anderson
3230e9537d Port new Thumb1 encoding tests over to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:37:33 +00:00
Jim Grosbach
37f88c7812 ARM assembly parsing and encoding test for BKPT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:11:13 +00:00
Jim Grosbach
5b657de62b ARM assembly parsing and encoding test for BIC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:00:53 +00:00
Jim Grosbach
395b453bed Thumb assembly parsing and encoding for B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:57:40 +00:00
Jim Grosbach
00f5d98205 Thumb assembly parsing and encoding for ASR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:49:09 +00:00
Jim Grosbach
5a1cd045cd Thumb assembly parsing and encoding for ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:37:40 +00:00
Jim Grosbach
53727fc659 Add a couple of FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:35:57 +00:00
Owen Anderson
4c81cf5dfc Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:21:36 +00:00
Jim Grosbach
358499ea3b Thumb assembly parsing and encoding for ADC(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:55:28 +00:00
Jim Grosbach
b1ee18ee69 Add missing '@' delimiter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:46:01 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Jim Grosbach
89e2aa6afd Thumb ADD(immediate) parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:57:34 +00:00
Jim Grosbach
194bd89829 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:20:01 +00:00
Jim Grosbach
3912b73c74 Thumb assembly parsing and encoding for ADD(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:34:08 +00:00
Jim Grosbach
c2408d3ce5 Add testcase for r137746. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:11:21 +00:00
Jim Grosbach
be2ac8ca7b Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:55:41 +00:00
Jim Grosbach
47a0d52b69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:45:50 +00:00
Jim Grosbach
d0d3f7e01f ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 17:06:20 +00:00
Owen Anderson
a9c989d55a Add a test file for Thumb2 NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes
1deddbbd56 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:36:45 +00:00
Owen Anderson
c4bda5633a Add some more comprehensive VFP decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 21:29:01 +00:00
Owen Anderson
c537f3be0c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:51:32 +00:00
Owen Anderson
95d01b8898 Add a test for Thumb1 LDRSH decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:15:43 +00:00
Owen Anderson
bd37b721c8 Add testcase for STRH. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:12:03 +00:00
Owen Anderson
5df7ef6cdb Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53 Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 18:44:44 +00:00
Owen Anderson
0d09499cf3 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 20:36:11 +00:00
Owen Anderson
a211c2c7e9 Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 19:42:45 +00:00
Jim Grosbach
7a8729effc Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:43:31 +00:00
Jim Grosbach
46c38aff89 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:01:02 +00:00
Benjamin Kramer
0d46ccfc5c MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 01:51:29 +00:00
Jim Grosbach
29e7b7deb4 Clean up formatting a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:57:17 +00:00
Jim Grosbach
857e1a7b3f ARM vector compare to zero instruction assembly parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:51:13 +00:00
Jim Grosbach
c69c26d95e Fix tests per now-correct encoding as of r137371. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:31:48 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:18:00 +00:00
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Jim Grosbach
2ef8241ce7 ARM STRHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:39:41 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Owen Anderson
9fe72bcd37 Improve operand validation for Thumb2 addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Jim Grosbach
961afdf1b6 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:43:42 +00:00
Jim Grosbach
534de6cad8 ARM STRB assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:42:58 +00:00
Jim Grosbach
c15bd92d2f Fix a copy/paste error so that LDRB(register) actually gets tested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:34:23 +00:00
Jim Grosbach
f91c14920c ARM STR(register) assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:26:17 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:07:11 +00:00
Jim Grosbach
f8fce711e8 ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:35:48 +00:00
Jim Grosbach
64104f48f2 ARM tests for LDRSHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:18:30 +00:00
Jim Grosbach
e0109c07ff ARM tests for LDRSH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:12:25 +00:00
Jim Grosbach
7d179b59cd ARM tests for LDRSBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:08:56 +00:00
Jim Grosbach
5e92159400 ARM tests for LDRSB assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:06:44 +00:00
Jim Grosbach
263bb07135 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137265 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:56:43 +00:00
Jim Grosbach
de2f526c7c ARM tests for LDRHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:55:38 +00:00
Jim Grosbach
46b355479f ARM tests for LDRH(register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:45:42 +00:00
Jim Grosbach
623a454b0f ARM LDRH(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:42:16 +00:00
Jim Grosbach
c7de52fcff Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:20:38 +00:00
Jim Grosbach
251bf25e7e ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 21:56:18 +00:00
Jim Grosbach
2fd2b87ded ARM LDRD(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 20:29:19 +00:00
Owen Anderson
8533ebad6f Add initial support for decoding NEON instructions in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 19:01:10 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 00:03:03 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:33:27 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:28:47 +00:00
Jim Grosbach
bc6fc20fcc ARM parsing and encoding for LDRB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:37:06 +00:00
Jim Grosbach
8668a5b0c8 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:11:33 +00:00
Jim Grosbach
0d6fac36ed ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 21:28:30 +00:00
Jim Grosbach
6fc1c08635 Add ARM LDR parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 20:33:39 +00:00
Rafael Espindola
5c4e52e496 Fix the bitwidth of the remaining fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 17:00:11 +00:00
Rafael Espindola
251a2bbfb0 print st_shndx with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:50:13 +00:00
Rafael Espindola
67ac0c0d63 print st_other with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:38:19 +00:00
Rafael Espindola
71a8f5ca12 print st_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:24:00 +00:00
Rafael Espindola
d7c278326f Print st_bind with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:10:35 +00:00
Rafael Espindola
a83f8ef9b4 Print r_sym with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:48:27 +00:00
Rafael Espindola
f81f6758f3 Print r_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:39:30 +00:00
Rafael Espindola
65ad8dc807 Another counter goes decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:27:46 +00:00
Rafael Espindola
f7179de2a5 Change anther counter to decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:01:03 +00:00
Rafael Espindola
014180d387 Don't print a counter in hex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 13:39:15 +00:00
Rafael Espindola
d7c9b63b58 Print all the bits in the addend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136867 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 13:00:24 +00:00
Jason W Kim
e651983e71 Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 00:38:45 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:50:40 +00:00
Jim Grosbach
e1cf5902ec ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 20:26:09 +00:00
Jim Grosbach
2c6363a62d ARM assembly parsing and encoding for RFE instruction. 
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 18:47:24 +00:00
Jim Grosbach
71d3d67508 ARM update tests for CPS instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-29 17:39:27 +00:00
Jim Grosbach
c5b3c58ae8 CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 21:59:38 +00:00
Jim Grosbach
cf121c35c4 ARM assembly parsing and encoding for BLX (immediate). 
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 21:57:55 +00:00
Jim Grosbach
43afb6ff1c Remove obsolete FIXME reference in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 21:37:05 +00:00
Jim Grosbach
293a2ee306 ARM assembly parsing and encoding for BFC and BFI. 
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 21:34:26 +00:00
Jim Grosbach
70a0915cd1 ARM parsing and encoding for ADR. 
The label does not have a '#' prefix. Add parsing and encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 16:33:54 +00:00
Jim Grosbach
19b9d6912a Update ARM tests for parsing and encoding of WFE, WFI and YIELD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 16:00:41 +00:00
Jim Grosbach
8050a61914 ARM parsing and encoding tests. 
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 00:37:03 +00:00
Evan Cheng
5de728cfe1 Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:22:03 +00:00
Jim Grosbach
ed398468b5 ARM assembly parsing and encoding for USUB16 and USUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:10:05 +00:00
Jim Grosbach
953e2e81de ARM assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:07:00 +00:00
Kevin Enderby
c37d4bbf1f Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:01:50 +00:00
Jim Grosbach
fc2eb31a3c Clean up tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:35:06 +00:00
Jim Grosbach
addec77b54 ARM assembly parsing and encoding support for USAT and USAT16. 
Use range checked immediate operands for instructions. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:34:17 +00:00
Jim Grosbach
5f33d13da4 ARM assembly parsing and encoding tests for USAD8 and USADA8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:23:02 +00:00
Jim Grosbach
144da2c8f0 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:13:08 +00:00
Jim Grosbach
41438398c1 Fix comment copy/paste-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:11:41 +00:00
Jim Grosbach
29e85bc728 ARM assembly parsing and encoding tests for UQASX and UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:09:30 +00:00
Jim Grosbach
24a541b79f ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:08:14 +00:00
Jim Grosbach
49f2ceddd2 ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:01:42 +00:00
Jim Grosbach
71725a099e ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:58:11 +00:00
Jim Grosbach
2adba4156b ARM assembly parsing and encoding tests for UMAAL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:53:42 +00:00
Jim Grosbach
f36b0a2ee4 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:21:59 +00:00
Jim Grosbach
66c8982244 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:20:45 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:09:25 +00:00
Jim Grosbach
b6854ad2b1 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:43:44 +00:00
Jim Grosbach
8b3fd56e0f ARM assembly parsing and encoding tests for TST instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:38:58 +00:00
Jim Grosbach
f1ae78af17 ARM assembly parsing and encoding tests for TEQ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:37:36 +00:00
Owen Anderson
06470311c5 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:29:48 +00:00
Jim Grosbach
7e1547ebf7 ARM assembly parsing and encoding for extend instructions. 
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:15:40 +00:00
Jim Grosbach
189610f946 ARM diagnostics for ldrexd/stredx out of order paired register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:25:39 +00:00
Jim Grosbach
36711e4a3c ARM parsing and encoding tests for load/store exclusive instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:07:21 +00:00
Jim Grosbach
4f6f13db1a ARM assembly parsing and encoding for SWP[B] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 17:15:11 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 16:24:27 +00:00
Jim Grosbach
873db3eeba ARM assembly parsing and encoding tests for SUB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:44:05 +00:00
Jim Grosbach
a46c658c66 Update ARM STM tests. Fix check: prefix for diagnostic tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:41:22 +00:00
Jim Grosbach
185f92e7d0 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:32:14 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:09:14 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction. 
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 22:20:28 +00:00
Jim Grosbach
f2a35fbd60 Move some ELF directives into ELF asm parser. 
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.

rdar://9827089


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 17:55:35 +00:00
Jim Grosbach
6ab4e3dd23 Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:15:38 +00:00
Jim Grosbach
0e76edf8c0 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:13:00 +00:00
Jim Grosbach
bf2845c0d8 ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:06:05 +00:00
Jim Grosbach
6808f21757 ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:34:56 +00:00
Jim Grosbach
44a456332f ARM assembly parsing and encoding tests for SMLAWB/SMLAWT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:51:24 +00:00
Jim Grosbach
ce501030d9 ARM assembly parsing and encoding tests. 
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:30:40 +00:00
Jim Grosbach
b544f68b70 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:18:21 +00:00
Jim Grosbach
b206daaec1 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:11:20 +00:00
Jim Grosbach
0ffd4a09df ARM testcases for assembly parsing and encoding SMLA* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:01:34 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:13:31 +00:00
Jim Grosbach
248e6c328c ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:04:48 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:44:50 +00:00
Jim Grosbach
9076b6e8f4 ARM assembly parsing and encoding tests for SEL instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 16:59:33 +00:00
Jim Grosbach
8409f04731 ARM parsing and encoding tests for SBC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:03:59 +00:00
Jim Grosbach
8ae45af794 ARM testcases for SADD/SASX parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:00:49 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:37:43 +00:00
Jim Grosbach
616fbdf987 ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:29:23 +00:00
Jim Grosbach
a4c34ab544 ARM parsing and encodings tests for saturating arithmetic insns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:18:28 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:57:11 +00:00
Jim Grosbach
61b1b21e9a Add tests for ARM PKH assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 19:02:03 +00:00
Eli Friedman
a4d0bd84f7 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:36:11 +00:00
Jim Grosbach
88d1bc832c Add parsing/encoding tests for ARM ORR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:48:53 +00:00
Jim Grosbach
a678514459 Consolidate ARM NOP encoding test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:39:38 +00:00
Jim Grosbach
c3635c2e92 ARM parsing and encoding tests for MVN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:20:31 +00:00
Jim Grosbach
b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:59:29 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:35:35 +00:00
Jim Grosbach
2317fe1584 Move mr[r]c[2] ARM tests and tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:28:56 +00:00
Jim Grosbach
1a2be4db5b ARM testcases for MOVT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:23:25 +00:00
Jim Grosbach
5f16057d1e ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:10:31 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:13:28 +00:00
Jim Grosbach
0ec2aa21d0 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:02:39 +00:00
Eli Friedman
7105259ce8 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 02:41:28 +00:00
Eli Friedman
5232cc675c PR10370: Make sure we know how to relax push correctly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 21:28:39 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 18:46:47 +00:00
Jim Grosbach
33c16a2737 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 22:04:21 +00:00
Jim Grosbach
70d8fcfaa0 Add some testcases for ARM MLA/MLS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:43:05 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:19:17 +00:00
Jim Grosbach
1134be2428 Enable some tests we now handle correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:02:23 +00:00
Jim Grosbach
3b14a5c546 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:35:38 +00:00
Jim Grosbach
791feea100 ARM ISB assembly parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:02:25 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:00:31 +00:00
Jim Grosbach
00a66653cb ARM tests for EOR instruction parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:22:21 +00:00
Jim Grosbach
6a86feafa8 Remove duplicate tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:19:19 +00:00
Jim Grosbach
e77494e3e3 ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:18:13 +00:00
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:40:38 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:59:38 +00:00
Jim Grosbach
14ab1c3387 ARM parsing and encoding tests for CMN/CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:26:58 +00:00
Jim Grosbach
d986bc66bc Shuffle ARM assembly tests a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:19:10 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:01:08 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:14:23 +00:00
Jim Grosbach
f333d471d2 Testcases for ARM assembly BX/BXJ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:46 +00:00
Jim Grosbach
37023b05c8 Testcases for ARM assembly BLX/BL instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:10:10 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd Fix copy-pasto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370 Add tests for ARM parsing of 'BIC' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96 Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:10:23 +00:00
Jim Grosbach
59642c2600 Add tests for ARM parsing of 'AND' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74 Add tests for ARM parsing of 'ADD' instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:50:29 +00:00
Jim Grosbach
dc89561fec Add check for predicate w/o S bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-12 16:25:04 +00:00
Jim Grosbach
3f00e31706 Fix recognition of ARM 'adcs' mnemonic. 
The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 17:09:57 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates. 
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 16:48:36 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo 
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-11 03:57:24 +00:00
Evan Cheng
3286920505 Add support for ARM / Thumb mode switching with .code 16 and .code 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 22:36:29 +00:00
Evan Cheng
39dfb0ff84 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 03:55:05 +00:00
Kevin Enderby
d7c7e2ff7d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 17:55:20 +00:00
Kevin Enderby
d521f2d2f1 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a 
push with a small constant produces a 2-byte push.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 17:23:46 +00:00
Eli Friedman
af45b3d8cb Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-05 18:21:20 +00:00
Joerg Sonnenberger
ca0ede7655 Recognize the xstorerng alias for VIA PadLock's xstore instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 01:38:03 +00:00
Jim Grosbach
254cf03a45 Asm parser range checking on .<size> <value> directives. 
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-29 16:05:14 +00:00
Jim Grosbach
adf7366771 ARM Thumb2 asm syntax optional destination operand for binary operators. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 00:19:13 +00:00
Jim Grosbach
6b8f1e35ea ARM Assembly support for Thumb mov-immediate. 
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 23:54:06 +00:00
Jim Grosbach
fbd01783a6 ARM assembler support for ldmfd/stmfd mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 20:32:18 +00:00
Jim Grosbach
0d06bb9548 ARM assembler support for vpush/vpop. 
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 20:00:07 +00:00
Jim Grosbach
0ff9220ccb ARM Assembly syntax support for arithmetic implied dest operand. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 19:09:15 +00:00
Jim Grosbach
75c2b2028b Move ARM-specific test to ARM directory. 
Hopefully make the x86-target-only Windows bots happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-25 01:53:17 +00:00
Jim Grosbach
56fc642000 Testcase for r133818 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133823 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 20:59:01 +00:00
Eli Friedman
a390a1aa48 Add support for movntil/movntiq mnemonics. Reported on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-23 21:07:47 +00:00
Nick Lewycky
94d4c91bc5 Add support for assembling "movq" when it's correct to do so, while continuing 
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-21 22:45:41 +00:00
Bob Wilson
38c892624b Revert r133452: "Emit movq for 64-bit register to XMM register moves..." 
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-21 17:35:13 +00:00
Nick Lewycky
1bd15700a0 Emit movq for 64-bit register to XMM register moves, but continue to accept 
movd when assembling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-20 18:33:26 +00:00
Hans Wennborg
5cc6491f50 MC: Allow .common as alias for .comm assembler directive. PR10116. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-18 13:51:54 +00:00
Bill Wendling
393c4047c0 Improve the heuristic to emit the alias if the number of hard-coded registers 
are also greater than the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 04:31:19 +00:00
Bill Wendling
740e5b3586 Heuristic: If the number of operands in the alias are more than the number of 
operands in the aliasee, don't print the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 03:17:20 +00:00
Roman Divacky
be234dabf4 Test that ".byte 1, 2, 3, 4" does the right thing. 
Requested by nbjoerg!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132716 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 17:32:17 +00:00
Rafael Espindola
6536644713 Basic support for macros with explicit arguments. 
We still don't handle

* default values
* :req
* :vararg
* \()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-05 02:43:45 +00:00
Nick Lewycky
e0b87032f5 Add support for @GOTPTOFF in i386 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 03:33:27 +00:00
Rafael Espindola
04507f062f Use %rbp on a 64 bit test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 04:04:50 +00:00
Benjamin Kramer
06a8d54967 Move ARM specific test into the ARM subdir. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes
be64b39431 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:46:09 +00:00
Charles Davis
88c816453f Add the suffix to the Win64 EH data sections' names if given. Add a test for 
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 21:38:47 +00:00
Charles Davis
07cbe23173 Assorted fixes for Win64 EH unwind info emission: 
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.

Add a test for the latter two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132188 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 15:10:25 +00:00
Charles Davis
3a5d7d0665 Add a test for Win64 EH unwind information emission. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 03:54:43 +00:00
Charles Davis
3ac7b034d6 Add a test for the chained directives that I forgot last time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 05:17:43 +00:00
Charles Davis
ca93138e11 Test .seh_startchained and .seh_endchained parsing. 
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.

The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 02:45:47 +00:00
Charles Davis
410ef2b263 Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with 
them.

I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:43:45 +00:00
Charles Davis
575630ccb8 Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the 
buggy methods that parse these directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:51:25 +00:00
Charles Davis
47268164f3 Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another 
one I found by inspection).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:08:15 +00:00
Charles Davis
309213279e Add a test for the .seh_handler directive. Fix problems with the parsing 
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
56926a3961 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 00:35:03 +00:00
Charles Davis
40de0e013a Test basic SEH directive-parsing functionality. Fix a latent bug exposed by 
this test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 21:22:53 +00:00
Chris Lattner
d521d8bf92 add test from PR9164 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 22:35:34 +00:00
Chris Lattner
b8a21ad915 testcase for PR9378 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 22:32:53 +00:00
Johnny Chen
75f4296c7c Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 17:51:04 +00:00
Rafael Espindola
b8adb8af0f adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea fixes target address tBL and tBLX and sets relocation type 
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:01:01 +00:00
Jason W Kim
861b9c6a39 This fixes one divergence between LLVM and binutils for ARM in the 
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. 
Fixes PR9934.

We really need to start tblgening the relocation info :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:32:34 +00:00
Johnny Chen
a96581f4f7 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 20:32:41 +00:00
Rafael Espindola
6469540adf sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 16:17:21 +00:00
Owen Anderson
18901d63bf Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 17:00:48 +00:00
Rafael Espindola
e3a0e987f3 On MachO, unlike ELF, there should be no relocation to produce the CIE pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131149 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 20:59:42 +00:00
Rafael Espindola
0d450dc659 In a debug_frame the cfi offset is to the start of the debug_frame section! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 15:20:23 +00:00
Rafael Espindola
40a7dbbeff Add support for producing .deubg_frame sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen
f695b3ad62 Explicitly request -join-physregs for some tests that depend on it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:01:59 +00:00
Eric Christopher
b65122c873 Remove some random comments that snuck in from somewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 00:48:02 +00:00
Eric Christopher
2fc496fcf5 xmm0 is an implicit parameter in this and so shouldn't be in the 
string template.

Fixes rdar://8493866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 01:28:32 +00:00
Daniel Dunbar
c8497b6a25 MCAsmLayout: Add support for computing the symbol offset of variables. Not 
currently used, because variables don't get reported as being "defined".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 18:20:20 +00:00
Daniel Dunbar
90604ab725 MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 18:20:17 +00:00
Johnny Chen
5a2336e794 Add tests for A8.6.110 NOP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 23:29:21 +00:00
Chandler Carruth
a4a2a03c31 Remove some hard coded CR-LFs. Some of these were the entire files, one of 
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-25 07:11:23 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 19:12:43 +00:00
Rafael Espindola
1ac7fe0f4d Fix relative relocations. This is sufficient for running the rust testsuite with 
MC :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129923 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 18:36:50 +00:00
Rafael Espindola
3660a847f1 Behave like gnu as when a relocation crosses sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 14:01:45 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354 A8.6.315 VLD3 (single 3-element structure to all lanes) 
The a bit must be encoded as 0.

rdar://problem/9292625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:49:08 +00:00
Joerg Sonnenberger
c25e8d8cea Add encoding tests for flds/filds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 19:25:31 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Johnny Chen
de29a52940 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 
(single element or n-element structure to all lanes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:10:45 +00:00
Johnny Chen
cd695fdac1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 19:13:28 +00:00
Bill Wendling
d336de318e As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias 
(movzx/movsx) because they give more information. Revert that part of the patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 01:46:37 +00:00
Bill Wendling
c6df9883da Have the X86 back-end emit the alias instead of what's being aliased. In most 
cases, it's much nicer and more informative reading the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 01:11:51 +00:00
Johnny Chen
e8d087ad35 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:04:32 +00:00
Johnny Chen
9bb386a933 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 17:51:02 +00:00
Johnny Chen
55e6419b12 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:31:00 +00:00
Johnny Chen
ec51a6225c The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 17:09:04 +00:00
Rafael Espindola
25f492e778 Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 16:12:03 +00:00
Rafael Espindola
c57543964d Implement .cfi_same_value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 15:31:05 +00:00
Johnny Chen
163b6eaf25 Add one test case (svc). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:21:48 +00:00
Eric Christopher
05f9e4e8bd Match case for invalid constant error messages and add a new 
test for invalid hexadecimals.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:18:03 +00:00
Johnny Chen
e77f72d7d2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:14:49 +00:00
Eric Christopher
164254d77c Test for invalid constant expr addition - bad octal constant. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:03:38 +00:00
Johnny Chen
de16508955 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 23:33:30 +00:00
Rafael Espindola
a61842bf6e Implement cfi_rel_offset 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:49:50 +00:00
Rafael Espindola
787d41aaa0 Add test for previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:41:34 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00
Chris Lattner
15f8951799 fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, 
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 19:41:05 +00:00
Benjamin Kramer
c18214a6e0 Don't store Twine temporaries, it's not safe. 
And don't append the name over and over again in the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-09 11:26:27 +00:00
Johnny Chen
c636074afc Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:18:07 +00:00
Johnny Chen
084b5df5ae MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 
Add tests for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 17:29:58 +00:00
Johnny Chen
97fdff1d3f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 00:29:09 +00:00
Rafael Espindola
9974b8b3cb Update tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 23:51:25 +00:00
Johnny Chen
3cf3059b11 Add a VEXT test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 22:04:01 +00:00
Rafael Espindola
ce8463f1fb Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:26:23 +00:00
Johnny Chen
22dc4d9f59 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b Add sanity checking for invalid register encodings for saturating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:02:08 +00:00
Johnny Chen
4d4e25740b Add some more comments about checkings of invalid register numbers. 
And two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 18:33:19 +00:00
Johnny Chen
f16f4e09ec Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:37:34 +00:00
Johnny Chen
8424a60fc9 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 01:05:52 +00:00
Johnny Chen
2455268cdd Should also check SMLAD for invalid register values. 
rdar://problem/9246650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:50:25 +00:00
Johnny Chen
d8b4c4d74f A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 22:14:48 +00:00
Johnny Chen
4d81c9a6ba A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 20:49:02 +00:00
Johnny Chen
a9611549fe Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 18:27:46 +00:00
Johnny Chen
6a1220eeca Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-06 01:18:32 +00:00
Johnny Chen
2c868d1eef Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:28:00 +00:00
Johnny Chen
c3281c10c9 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:57:07 +00:00
Johnny Chen
5438d76416 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:18:07 +00:00
Johnny Chen
c584e317e9 ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 21:49:44 +00:00
Johnny Chen
2c2130bc64 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 20:32:23 +00:00
Johnny Chen
bbc65bbb90 ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 19:42:11 +00:00
Johnny Chen
5dc0c50372 LDRD now prints out two dst registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:53:14 +00:00
Johnny Chen
12bb2958c4 Constants with multiple encodings (ARM): 
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 18:02:46 +00:00
Johnny Chen
b26d8d7c49 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 17:43:10 +00:00
Johnny Chen
157536b1fb Fix SRS/SRSW encoding bits. 
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 00:16:18 +00:00
Johnny Chen
2d66cec9dd Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
ac79e4c82f - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 17:18:19 +00:00
Joerg Sonnenberger
4a8ac8de1d Add support for the VIA PadLock instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-04 16:58:13 +00:00
Johnny Chen
04187ecd57 Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:24:54 +00:00
Johnny Chen
103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:32:51 +00:00
Johnny Chen
ec30f6f5e5 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:21:38 +00:00
Johnny Chen
5307da994a Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes
ae0855401b Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:26:08 +00:00
Johnny Chen
0c630b5f38 Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which 
amounts to an UNDEFINED instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 20:54:30 +00:00
Johnny Chen
a52d7da1d8 Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:28:35 +00:00
Johnny Chen
8901e6ff3d Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:53:50 +00:00
Daniel Dunbar
48a36158ec Remove stray empty test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:01:56 +00:00
Bruno Cardoso Lopes
b41aaab5a1 Revert r128632 again, until I figure out what break the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
bcd3a9cd84 Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" 
This revision introduced a dependency cycle, as nlewycky mentioned by email.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 00:39:16 +00:00
Bruno Cardoso Lopes
40829ed6f5 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and 
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 23:32:32 +00:00
Johnny Chen
caee968481 Add a test case for thumb stc2 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-30 01:02:06 +00:00
Kevin Enderby
b715ce35d7 Adding a test for "-inf" as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:54:10 +00:00
Johnny Chen
e077157e54 Add a test case for MSRi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:52:02 +00:00
Kevin Enderby
360d8d7a02 Added support symbolic floating point constants in the MC assembler for Infinity 
and Nans with the same strings as GAS supports.  rdar://8673024


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:11:52 +00:00
Johnny Chen
5726005e4f Add a thumb test file for printf (iOS 4.3). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 21:09:30 +00:00
Johnny Chen
9eda569a74 A8.6.188 STC, STC2 
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:49:38 +00:00
Johnny Chen
4381dd1f21 Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:10:06 +00:00
Johnny Chen
288a4284bb Add and modify some tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 19:08:52 +00:00
Owen Anderson
848b0c39b1 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-29 16:45:53 +00:00
Daniel Dunbar
c6cf43d258 MC: Add support for disabling "temporary label" behavior. Useful for debugging 
on Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128430 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-28 22:49:15 +00:00
Johnny Chen
d560a80925 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-28 18:41:58 +00:00
Johnny Chen
eca915fb52 Fixed the t2PLD and friends disassembly and add two test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-26 01:32:48 +00:00
Johnny Chen
cf0fe4650f Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 23:02:58 +00:00
Johnny Chen
65c0a59869 Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 22:43:28 +00:00
Johnny Chen
a2755b9829 Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 19:35:37 +00:00
Johnny Chen
b66a097612 A8.6.226 TBB, TBH: 
Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 18:40:21 +00:00
Johnny Chen
ceceabd4b1 Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 18:29:49 +00:00
Daniel Dunbar
8b2b43c41d MC: Improve some diagnostics on uses of '.' pseudo-symbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:47:17 +00:00
Johnny Chen
6c3891067b Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. 
rdar://problem/9184053


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a Also need to handle invalid imod values for CPS2p. 
rdar://problem/9186136


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:03:12 +00:00
Johnny Chen
a7078c4f27 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:09:48 +00:00
Johnny Chen
ef74e9ab40 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 00:17:42 +00:00
Johnny Chen
8c13335c9a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:42:31 +00:00
Johnny Chen
1090d7711b The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:21:14 +00:00
Johnny Chen
c39b6271be Handle the added VBICiv*i* NEON instructions, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:04:39 +00:00
Johnny Chen
9091bf25d9 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f Plug a leak in the arm disassembler and put the tests back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:04:58 +00:00
Johnny Chen
02af767dca Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. 
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:56:23 +00:00
Johnny Chen
e6d69e7dbe ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:42:48 +00:00
Johnny Chen
b4ac342ea0 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 17:04:22 +00:00
Johnny Chen
3d793962be Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 00:28:38 +00:00
Johnny Chen
8d668a8605 Add disassembly test cases for: 
A8.6.292 VCMPE


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 23:08:56 +00:00
Johnny Chen
27c6baeca2 LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 22:28:49 +00:00
Johnny Chen
83cf2ffdcd Add one more test case for VFP Load/Store Multiple (vpop). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 20:21:08 +00:00
Johnny Chen
758df29741 A8.6.399 VSTM: 
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-22 20:00:10 +00:00
Rafael Espindola
7c18fa87a4 Write the section table and the section data in the same order that 
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-20 18:44:20 +00:00
Johnny Chen
94dad03a96 Fixed an assert by the ARM disassembler for LDRD_PRE/POST. 
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-19 01:16:20 +00:00
Owen Anderson
0082830cb2 Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 22:50:18 +00:00
Joerg Sonnenberger
96622aa063 Support explicit argument forms for the X86 string instructions. 
For now, only the default segments are supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 11:59:40 +00:00
Johnny Chen
5e5a40867a The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. 
Remove the offending logic and update the test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-18 00:38:03 +00:00
Johnny Chen
e68d8ec252 It used to be that t_addrmode_s4 was used for both: 
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 22:04:05 +00:00
Daniel Dunbar
8d06ffca9b MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have 
been removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 16:25:24 +00:00
Joerg Sonnenberger
d02c8b6cc1 Fix handling of @IDNTPOFF relocations, they need to get STT_TLS. 
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-17 00:35:10 +00:00
Johnny Chen
276f6f9cf9 There were two issues fixed: 
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 22:27:33 +00:00
Sean Callanan
9a9d8b9732 Basic sanity checks to ensure that 2- and 3-byte 
VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 01:32:46 +00:00
Johnny Chen
085ea1b633 Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra 
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 01:13:17 +00:00
Cameron Zwarich
899eaa3569 Roll r127459 back in: 
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 21:52:04 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get 
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 19:30:30 +00:00
Cameron Zwarich
592ca3fda9 Optimize trivial branches in CodeGenPrepare, which often get created from the 
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 04:54:27 +00:00
Johnny Chen
18b475f954 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 20:01:14 +00:00
Bill Wendling
620d0cc7ac * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 00:33:17 +00:00
Bill Wendling
c04a9dea78 Correct the encoding for VRSRA and VSRA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-09 00:00:35 +00:00
Bill Wendling
7c6b608a7c * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 23:48:09 +00:00
Bill Wendling
591432136c A few more tests for instruction encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 02:51:48 +00:00
Bill Wendling
3116dce338 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 23:38:41 +00:00
Joerg Sonnenberger
89e0f386f3 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:03:14 +00:00
Eli Friedman
86d822df6d Followup to r126970: add 64-bit encoding tests for str with reg operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 04:06:47 +00:00
Eli Friedman
ac39bd534b PR9377: Handle x86 str with register operand in a way consistent with gas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 00:10:17 +00:00
Joerg Sonnenberger
ea83b13350 Bug#9033: For the ELF assembler output, always quote the section name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:31:08 +00:00
Eli Friedman
78c1e1781c PR9352: Always emit a relocation for weak symbols. Not emitting relocations 
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:24:36 +00:00
Bob Wilson
1473f35c47 TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:19:52 +00:00
Bob Wilson
181d3fe727 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 01:41:01 +00:00
Kevin Enderby
d39647d913 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:08:33 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Kevin Enderby
d436d5b1c9 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:46:31 +00:00
Chris Lattner
98ea4ce516 split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 19:06:35 +00:00
Joerg Sonnenberger
93c65e6e66 Restore r125595 (reverted in r126336) with modifications: 
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 21:59:22 +00:00
Devang Patel
3fe3424a21 Move arch specific tests in arch specific directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 19:06:27 +00:00
Jim Grosbach
f956183643 Remove file. Previous commit deleted content, but left the file around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 21:43:31 +00:00
Jim Grosbach
33b7bebca4 Revert r125595, which is an X86-only undocumented assembly syntax extension 
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.

Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 21:26:51 +00:00
Rafael Espindola
21451e533f Put in the symbol table symbols only used in a .globl statement. 
Fixes PR9292.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 20:22:07 +00:00
Sean Callanan
8fbc00b5ba Fixed a bug in the enhanced disassembler that caused 
it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 03:31:28 +00:00
Joerg Sonnenberger
00743c2218 Use the same (%dx) hack for in[bwl] as for out[bwl]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 20:40:09 +00:00
Sean Callanan
ec243ae2b8 Added a testcase for the enhanced disassembly bug 
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 02:19:18 +00:00
Joerg Sonnenberger
d86f482e4a Recognize loopz and loopnz as aliases for loope and loopne. 
From Dimitry Andric.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 00:43:07 +00:00
Rafael Espindola
87ca0e077d Implement xgetbv and xsetbv. 
Patch by Jai Menon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 00:35:18 +00:00
Joerg Sonnenberger
d45e8bf93b Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-21 23:25:41 +00:00
Rafael Espindola
f7ad048f1e Add some limited support for labels in org directives. Hopefully enough to fix 
PR9245.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-20 20:20:07 +00:00
Chris Lattner
824a9076ea implement PR9264: disambiguating 'bt mem, imm' as a btl. 
This is reasonable to do since all bt-mem forms do the
same thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-19 21:06:36 +00:00
Bruno Cardoso Lopes
584bf7bb03 Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-18 19:45:59 +00:00
Joerg Sonnenberger
5ad596f9d2 Recognize monitor/mwait with explicit register arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-18 00:48:11 +00:00
Joerg Sonnenberger
97755a063e Recognize leavel and leaveq aliases for leave. 
Validate encoding of leave in 64bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-17 23:36:39 +00:00
Rafael Espindola
908159b46a Gas is very inconsistent about when a relaxation/relocation is needed. Do 
the right thing and stop trying to copy it. Fixes PR8944.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125648 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-16 03:25:55 +00:00
Rafael Espindola
7768a9dce1 Add support for pushsection and popsection. Patch by Joerg Sonnenberger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-16 01:08:29 +00:00
Roman Divacky
738a00eb86 Add support for parsing [expr]. 
This is submitted by Joerg Sonnenberger and fixes his PR8685.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125595 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-15 20:43:39 +00:00
Bruno Cardoso Lopes
a2b6e4151b Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-14 13:09:44 +00:00
Reid Kleckner
26f23100ac Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. 
These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-12 23:24:13 +00:00
Jim Grosbach
b9db0c50d8 Do AsmMatcher operand classification per-opcode. 
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-10 00:08:28 +00:00
Owen Anderson
971b83b67a Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-08 22:39:40 +00:00
Benjamin Kramer
0fd90bc12f Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-08 22:29:56 +00:00
Bruno Cardoso Lopes
706d946cfe Add support for parsing dmb/dsb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-07 22:09:15 +00:00
Jason W Kim
953a2a3dee Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage 
failures with relocations.

The code committed is a first cut at compatibility for emitted relocations in
ELF .o.

Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.

Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass

Added reminder fixme to tests for future conversion to .s form.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-07 01:11:15 +00:00
Jason W Kim
2d7a53aec2 Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to 
5 to match the current doc.
Added FIXME reminder Make it really configurable later.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-04 21:41:11 +00:00
Jason W Kim
685c350ae7 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. 
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-04 19:47:15 +00:00
Evan Cheng
4d98ee5234 Fix test for non-darwin targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 01:16:18 +00:00
Bob Wilson
d11c57a937 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 17:50:30 +00:00
Roman Divacky
14e66553d5 Add support for parsing .float 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 14:20:32 +00:00
Nico Weber
4c4c732960 PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124467 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 03:04:41 +00:00
Evan Cheng
c3a20bab75 Fix PLD encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:48:34 +00:00
Roman Divacky
54b0f4f2a4 Add support for specifying register name in cfi-register/offset/def 
as well as register number.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124379 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 17:16:37 +00:00
Bruno Cardoso Lopes
106df6da36 Add encoding testcases for ARM vcvtr variations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes
1b10d5be40 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:28:14 +00:00
Rafael Espindola
59b8cf4512 Jörg Sonnenberger noticed that we were missing this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124139 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 19:40:38 +00:00
Rafael Espindola
184640e96e Handle strings in section names the same way as gas: 
* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 18:02:54 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:55:27 +00:00
Rafael Espindola
54104db434 Add support for lowercase variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 16:11:25 +00:00
Rafael Espindola
0cf5e3d51d Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 05:43:40 +00:00
Bruno Cardoso Lopes
030160073d Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes
1115c47203 Add testcases for clz encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes
e47f3751d7 Fix the encoding and parsing of clrex instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
8dd37f7b7d Add cdp/cdp2 instructions for thumb/thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
b32f7a5f4b - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
6b3a999f22 Add mcr*2 and mr*c2 support to thumb2 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
fa5bd27fbe Add mcr* and mr*c support to thumb targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes
3abd75bf1d Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-19 16:56:52 +00:00
Owen Anderson
6cd0b17ba7 When matching asm operands, always try to match the most restricted type first. 
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes
61505907f5 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
e7255a80e3 Fix MRS encoding for arm and thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
892fc6d7b6 Fix the encoding of t2ISB by using the right class and also parse it correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
fdcee77887 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
a461d42228 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 20:45:56 +00:00
Daniel Dunbar
2e3cea3153 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-18 03:06:03 +00:00
Rafael Espindola
1c10db3da9 Update tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-16 18:02:57 +00:00
Evan Cheng
f3eb3bba16 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-14 02:38:49 +00:00
Owen Anderson
0fba714359 As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 22:38:16 +00:00
Evan Cheng
7597212abc Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-13 07:58:56 +00:00
Bill Wendling
7caebff83d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 21:20:59 +00:00
Jason W Kim
86a97f2e4d 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-12 00:19:25 +00:00
Jason W Kim
9081b4b4cf Workaround for bug 8721. 
.s Test added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 23:53:41 +00:00
Chris Lattner
3a5004dc3e Fix PR8946, a missing reg/reg form of movdqu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 17:04:55 +00:00
Daniel Dunbar
352e148cbe McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-11 15:59:50 +00:00
Daniel Dunbar
8ab1112bdc McARM: Flush out hard coded known non-predicated mnemonic list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-10 21:01:03 +00:00
Rafael Espindola
2f867a63da Correctly disassemble truncated asm. 
Patch by Richard Simth.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-06 16:48:42 +00:00
Evan Cheng
bbdcd44361 Convert MC tests to .s so codegen changes won't break them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-03 23:47:14 +00:00
Rafael Espindola
7a54997d67 Fix PR8878. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-01 19:05:35 +00:00
Nick Lewycky
c00210cef2 Add another non-commutable instruction that gas accepts commuted forms for. 
Fixes PR8861.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-30 22:10:49 +00:00
Daniel Dunbar
b2624eda5a MC/Mach-O/Thumb: Set the thumb bit in the symbol table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 14:14:06 +00:00
Rafael Espindola
caf1158b0f Correctly encode pcrel|indirect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122624 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 04:31:26 +00:00
Rafael Espindola
a7e450574c Fix bug when trying to output uint16_t or uint32_t. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 02:30:49 +00:00
Rafael Espindola
b40a71fda1 Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks 
like 6 is a fixed point of that and so the previous tests were OK :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 01:42:56 +00:00
Rafael Espindola
b4601bd2ff Implement cfi_def_cfa_register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 00:26:06 +00:00
Rafael Espindola
b790a17efb Initial .cfi_offset implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122611 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-29 00:09:59 +00:00
Rafael Espindola
3b78cdc57a Don't produce a "DW_CFA_advance_loc 0". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-28 23:38:03 +00:00
Rafael Espindola
fe024d0a62 Implement .cfi_remember_state and .cfi_restore_state. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-28 18:36:23 +00:00
Rafael Espindola
245a1e2041 Relax address updates in the eh_frame section. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-28 05:39:27 +00:00
Rafael Espindola
5bba084253 Start adding basic support for emitting the call frame instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122590 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-28 04:15:37 +00:00
Rafael Espindola
bdc3167c08 Add support for .cfi_lsda. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122584 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-27 15:56:22 +00:00
Daniel Dunbar
e862453806 MC/Mach-O/Thumb: Select appropriate relocation types for Thumb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122583 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-27 14:49:49 +00:00
Rafael Espindola
c3a561cb8e Handle reloc_riprel_4byte_movq_load. Should make the bots happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122579 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-27 02:03:24 +00:00
Rafael Espindola
3a83c40ab6 Add support for the same encodings of the personality function that gnu as 
supports.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-27 00:36:05 +00:00
Rafael Espindola
98976610d2 Add support for @note. Patch by Jörg Sonnenberger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122568 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-26 21:30:59 +00:00
Rafael Espindola
d7c8ccae8e Add basic support for .cfi_personality. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-26 20:20:31 +00:00
Chris Lattner
7ab3cc32d6 Generalize a previous change, fixing PR8855 - an valid large immediate 
rejected by the mc assembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-25 21:36:35 +00:00
Daniel Dunbar
4010dd72b8 MC/Mach-O/ARM: Start handling some Thumb branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122547 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-24 16:41:46 +00:00
Kevin Enderby
d82ed5b734 In llvm-mc parse a Hash token as a full line comment. Allows handling of 
preprocessed .s files and matches darwin gas.  rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-24 00:12:02 +00:00
Daniel Dunbar
72123334ad MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122441 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 21:26:43 +00:00
Rafael Espindola
ecbbf40d5c Add reduced test from 8845. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 21:15:13 +00:00
Daniel Dunbar
df561e0234 MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is 
esp. important given that the LOCAL_SECTDIFF enumeration got redefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 16:52:19 +00:00
Daniel Dunbar
294e67861c MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122407 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 16:19:24 +00:00
Rafael Espindola
f01212489b Simplify the handling of .size expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-22 16:03:00 +00:00
Wesley Peck
d66a32c35f Teach the MBlaze disassembler to disassemble special purpose registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122269 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 21:18:04 +00:00
Roman Divacky
d149186e15 Set the value of absolute symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 21:14:39 +00:00
Roman Divacky
1ae3c165f7 Print all 64bits for st_value and st_size. Adjust tests accordingly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 20:49:43 +00:00
Wesley Peck
9c0068f0a3 Teach the MBlaze asm parser how to parse special purpose register names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-20 20:43:24 +00:00
Roman Divacky
7529b16410 Add support for lexing single quotes like 'c'. 
This fixed 8615.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122150 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-18 08:56:37 +00:00
Rafael Espindola
54f08852f6 Add a test that shows that we produce no fixups when computing the difference 
of two symbols in the same fragment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122145 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-18 05:07:45 +00:00
Rafael Espindola
a5ff979c11 Test for push being relaxed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-18 01:16:59 +00:00
Daniel Dunbar
17304b3489 MC/Expr: Implemnt more aggressive folding during symbol evaluation using 
IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away
something like:
--
_a:
...
L0:
...
L1:
...
.long (L1 - L0) / 2
--

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 05:50:33 +00:00
Rafael Espindola
dfe125cc9c "Fix" FDE alignment to match what gas does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-17 00:28:02 +00:00
Rafael Espindola
3ee33aa6f9 Make pushq produce signed relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-16 22:50:01 +00:00
Bob Wilson
0406356cd4 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 22:14:12 +00:00
Bob Wilson
8d1b7e57e5 Fix misspelled target triples in MC/ARM test commands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 22:14:01 +00:00
Rafael Espindola
2bf6afc277 Relax alignment fragments. 
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 08:45:53 +00:00
Rafael Espindola
f9a4476173 Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments. 
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:39:29 +00:00
Kevin Enderby
53ef11884f Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:24:36 +00:00
Daniel Dunbar
abfbac52df MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 17:37:16 +00:00
Rafael Espindola
89b9372605 Fixed version of 121434 with no new memory leaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 07:39:47 +00:00
Rafael Espindola
f7fd4aa261 Revert my previous patch to make the valgrind bots happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-10 04:01:09 +00:00
Rafael Espindola
1c952b9cc9 Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 23:48:29 +00:00
Kevin Enderby
193c3acbe5 Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-09 19:19:43 +00:00
Kevin Enderby
76331754d4 Allow a slash, '/', as a prefix separator for X86. rdar://8741045 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-08 23:57:59 +00:00
Rafael Espindola
545b77ef50 Fix absolute recording of differences of symbols in two sections. Reduced from ctor_dtor_count-2.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 17:12:32 +00:00
Rafael Espindola
3b3148f864 Fix relocations with weak definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 05:57:28 +00:00
Rafael Espindola
bf60dad984 Fix pcrel relocations that cross sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 03:50:14 +00:00
Rafael Espindola
f10d2be573 Fix a crash reduced from gcc produced assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121085 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 01:09:54 +00:00
Owen Anderson
eb6779c5b9 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 00:45:21 +00:00
Rafael Espindola
0bbe0b440e Second try at making direct object emission produce the same results 
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 17:27:56 +00:00
Rafael Espindola
340a7a1c8f Don't use PadSectionToAlignment on windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-06 03:03:44 +00:00
Rafael Espindola
5d4918dbd1 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 03:21:47 +00:00
Rafael Espindola
767b1be390 Next step: Only pad debug_line when the target is darwin. Add a FIXME to avoid 
doing that if the target is darwin10 or newer.

This fixes
*) Direct object emission was producing objects without the workaround on
   darwin9.
*) Assembly printing was producing objects with the workaround on linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-04 00:31:13 +00:00
Jim Grosbach
d91f4e40e6 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 22:31:40 +00:00
Jim Grosbach
41ad0c4c73 When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-03 20:33:01 +00:00
Rafael Espindola
9f44724be0 Rename temporary symbols if they conflict with artificial symbols created 
by the assembler. This was blocking parsing any large .s produced by clang for
example.

Fixes PR8596.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 20:46:11 +00:00
Owen Anderson
9d63d90de5 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-01 19:18:46 +00:00
Owen Anderson
7f2abbf268 Add tests for more forms of Thumb2 loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120436 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 18:15:21 +00:00
Bill Wendling
ef4a68badb Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 07:44:32 +00:00
Owen Anderson
6af50f7dd1 Correct Thumb2 encodings for a much wider range of loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-30 00:14:31 +00:00
Owen Anderson
75579f739f Provide Thumb2 encodings for basic loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:44:32 +00:00
Benjamin Kramer
8ad87ab166 Fix some broken CHECK lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120332 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 22:34:55 +00:00
Bill Wendling
2f17bf2a44 Add more Thumb encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-29 01:07:48 +00:00